Hi The extended register width in add/adds/sub/subs/cmp instructions is not always the same as target register, it depends on both target register width and extension type. But in current implementation the extended register width is always the same as target register. We have noticed it can generate following wrong assembler code when compiled an internal application,
add x2, x20, x0, sxtw 3
The correct assembler should be
add x2, x20, w0, sxtw 3
On the other hand I noticed current gcc can only generate following
extension types: xtb, xth, xtw. In these cases the extended register
width can only be 'w'. So this patch changes the the extended register
size attribute to 'w'.
Passed regression tests on qemu without failure.
OK for trunk and 4.9 branch?
thanks
Guozhi Wei
2014-09-22 Guozhi Wei <car...@google.com>
* config/aarch64/aarch64.md (*adds_<optab><ALLX:mode>_<GPI:mode>):
Change the extended register width to w.
(*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*adds_<optab><mode>_multp2): Likewise.
(*subs_<optab><mode>_multp2): Likewise.
(*add_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_mult_<GPI:mode>): Likewise.
(*add_<optab><mode>_multp2): Likewise.
(*add_uxt<mode>_multp2): Likewise.
(*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*sub_<optab><mode>_multp2): Likewise.
(*sub_uxt<mode>_multp2): Likewise.
(*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise.
(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
2014-09-22 Guozhi Wei <car...@google.com>
* gcc.target/aarch64/subs3.c: Change the extended register width to w.
* gcc.target/aarch64/adds3.c: Likewise.
* gcc.target/aarch64/cmp.c: Likewise.
patch1
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patch2
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