On Thu, 2010-08-05 at 21:08 -0700, Andrew Poelstra wrote: > > My vision is this: the current drawing area will become a tabbed > drawing > area, with each tab a different Group. Each Group is a logically > connected > subset of the PCB - so for example, you might have a power supply > Group, > a USB port Group, an amplifier Group, etc.
I'm not sure I personally would use this feature.. I already pretty much shun PCB's layer group functionality as there are not enough colours to render everything clearly! However.. some thoughts: When on a particular group, the rest of the board could perhaps be rendered (partially?) de-saturated (greyed out)... so the designer working on the PSU section is aware which areas of the board are available for use. Transparency is already used to good effect in my GL version of PCB (which I've got plans, but currently no time, to work on merging back into mainline). An ever expanding internal list of layer groups is probably a bad idea. If we create a significant number of layer groups, it increases the number of layers which need to be inter checked for connectivity. I recall, (but could easily be wrong), that r-trees of objects are kept per layer, not per layer group.** ** Confusingly, PCB already has "layer groups", which consist of multiple "layers". A layer group is what ends up physically as a plane of copper in your produced board. Your terminology reverses the meaning, with a "layer group" consisting of logically grouped parts spanning multiple physical layers. I presume you intend to get rid of PCB's existing layer group functionality (good riddance IMO), however it would be less confusing to pick a new name. Perhaps "logical group". A further design choice to make is whether to identify parts as part of a logical group by separating completely different data-structures for each group (IMO not easy), or just add on a tagging means to identify which group a object in a layer data-structure belongs to. This could then form the search key for a query from the view.. in database-esque pseudo-explanation: View tab "safety critical" defined as: render_normal_colours("SELECT * where LOGICAL_GROUP is "psu" or LOGICAL_GROUP is "safety_interlock;") render_desaturated_colours("SELECT * where LOGICAL_GROUP isnot "psu" and LOGICAL_GROUP isnot "safety_interlock;") View tab "all" defined as: render_normal_colours("SELECT *;") You should be able to add tagging functionality to the core of PCB without needing to teach existing renderers too much about it. I'm guessing that the GUI view will be where most of the work occurs. It could also be incredibly useful when it comes to more intelligent DRC checks (if we ever get there). distance_check ("LOGICAL_GROUP=mains_connected", "LOGICAL_GROUP=SELV", ">12mm", "SELV Separation violation") distance_check ("LOGICAL_GROUP=!eht_psu_output", "LOGICAL_GROUP=eht_psu_output", ">30mm", "EHT PSU Separation violation") (Ignore the crummy syntax!) I've often wondered about the possibility of tagging PCB with a working voltage class for certain traces, simply as it would be a killer feature for people like me who (sometimes) work on power supplies etc.. working at high voltages. Clearance / creepage distances (although perhaps harder to check) are an IMPORTANT design rule check for this kind of work. Answers on a post card as to whether multiple group tags per object are allowed, or whether (as in unix groups), you must define enough groups to express the separations you want. Hope this has been of help. Check out the OpenGL version of PCB too, if you want to play with some transparent rendering. Thindraw / thindraw polygon mode on a board with polygons is particularly pretty. (Also, try with / without the solder mask on, ideally with a board "outline" layer defined). git://repo.or.cz/geda-pcb/pcjc2.git The branch you want is probably "before_pours". "master" is also good, but changes polygon semantics rather a lot! (Polygon -> pour, complete with island removal and separate continuity checking for each broken up, non-islanded piece). Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user