-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 CN wrote:
| ---------- | module latch1 (clk, d, q); | input clk, d; | output q; | reg q; | | always @ (clk or d) begin | if (clk == 1'b1) begin | q = d; | end | end | | endmodule | ---------- | | With the command line | iverilog -tfpga -parch=virtex latch1a.v | | get the errors: | latch1a.v:7: error: Asynchronous if statement is missing the else clause. | latch1a.v:6: internal error: is_asynchronous does not match sync_async results. | | Is this to be expected? What am I doing wrong? Icarus Verilog doesn't know how to synthesize latches. If you are just trying to simulate your program, then use the -tvvp flag instead. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFCwZn2rPt1Sc2b3ikRArRSAKCQ0vXXk9mDIW+BCyW99a8Vj2F5ZgCffy7I SLENJuSL81SHlrS6RXRN9CY= =lUon -----END PGP SIGNATURE-----