I'm working on fixing this patch as it doesn't apply cleanly to the current code.
It also fails to pipeline fetch for the corner case when the pipeline uses all the fetch bandwidth and you have reached the end of a cache block. It should start the fetch for the next cycle but won't. Probably not a huge deal for the default O3 that is 8-wide fetch/issue, but for anything reasonable/smaller this patch won't work. I'm looking into this without breaking anything else in the fetch stage (right now I'm hitting an assert in buildInst() ). Geoff > On Wed, May 25, 2011 at 12:58 AM, Gabe Black <gbl...@eecs.umich.edu>wrote: > >> >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.m5sim.org/r/718/#review1260 >> ----------------------------------------------------------- >> >> >> Have you run the regressions for the various ISAs with this patch? Have >> you tried the applicable ISAs with fetch pipelines deeper than the default >> (one stage?). The fetch code is subjected to a lot of corner cases and would >> likely be easy to break in subtle ways, so we need to be really careful. >> Also, have you considered making this an external component to the CPU? O3 >> is already very complicated, so if it could make sense to compartmentalize >> this as another component that would help. >> >> - Gabe >> >> >> On 2011-05-24 12:01:29, Lisa Hsu wrote: >> > >> > ----------------------------------------------------------- >> > This is an automatically generated e-mail. To reply, visit: >> > http://reviews.m5sim.org/r/718/ >> > ----------------------------------------------------------- >> > >> > (Updated 2011-05-24 12:01:29) >> > >> > >> > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and >> Nathan Binkert. >> > >> > >> > Summary >> > ------- >> > >> > Enabled instruction fetch pipelining. >> > >> > This patch is from one of our co-ops who has since finished her term, >> Yasuko Watanabe. I don't personally know much about it. In the end, I'll >> push in her name. Thanks. >> > >> > >> > Diffs >> > ----- >> > >> > src/cpu/o3/fetch.hh 54a65799e4c1 >> > src/cpu/o3/fetch_impl.hh 54a65799e4c1 >> > >> > Diff: http://reviews.m5sim.org/r/718/diff >> > >> > >> > Testing >> > ------- >> > >> > >> > Thanks, >> > >> > Lisa >> > >> > >> >> _______________________________________________ >> gem5-dev mailing list >> gem5-dev@m5sim.org >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
