changeset ce61b7a13407 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ce61b7a13407
description:
sparc: update simple cpu regressions
use stats file generated by zizzer
diffstat:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
| 42 +-
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
| 42 +-
tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
| 386 +-
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
| 42 +-
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 390 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
| 1206 ++++----
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 1496 +++++-----
7 files changed, 1802 insertions(+), 1802 deletions(-)
diffs (truncated from 3865 to 300 lines):
diff -r 30daf1dd5c91 -r ce61b7a13407
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt Wed Jun
08 11:58:09 2011 -0500
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt Fri Jun
10 03:45:24 2011 -0400
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4684 #
Simulator instruction rate (inst/s)
-host_mem_usage 195500 #
Number of bytes of host memory used
-host_seconds 1.14 #
Real time elapsed on the host
-host_tick_rate 2368799 #
Simulator tick rate (ticks/s)
-sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 5340 #
Number of instructions simulated
sim_seconds 0.000003 #
Number of seconds simulated
sim_ticks 2701000 #
Number of ticks simulated
-system.cpu.idle_fraction 0 #
Percentage of idle cycles
-system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 639191 #
Simulator instruction rate (inst/s)
+host_tick_rate 322368277 #
Simulator tick rate (ticks/s)
+host_mem_usage 216400 #
Number of bytes of host memory used
+host_seconds 0.01 #
Real time elapsed on the host
+sim_insts 5340 #
Number of instructions simulated
+system.cpu.workload.num_syscalls 11 #
Number of system calls
system.cpu.numCycles 5403 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
-system.cpu.num_busy_cycles 5403 #
Number of busy cycles
-system.cpu.num_conditional_control_insts 0 #
number of instructions that are conditional controls
+system.cpu.num_insts 5340 #
Number of instructions executed
+system.cpu.num_int_alu_accesses 4517 #
Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 #
Number of float alu accesses
+system.cpu.num_func_calls 146 #
number of times a function call or return occured
+system.cpu.num_conditional_control_insts 774 #
number of instructions that are conditional controls
+system.cpu.num_int_insts 4517 #
number of integer instructions
system.cpu.num_fp_insts 0 #
number of float instructions
+system.cpu.num_int_register_reads 10620 #
number of times the integer registers were read
+system.cpu.num_int_register_writes 4859 #
number of times the integer registers were written
system.cpu.num_fp_register_reads 0 #
number of times the floating registers were read
system.cpu.num_fp_register_writes 0 #
number of times the floating registers were written
-system.cpu.num_func_calls 0 #
number of times a function call or return occured
+system.cpu.num_mem_refs 1402 #
number of memory refs
+system.cpu.num_load_insts 724 #
Number of load instructions
+system.cpu.num_store_insts 678 #
Number of store instructions
system.cpu.num_idle_cycles 0 #
Number of idle cycles
-system.cpu.num_insts 5340 #
Number of instructions executed
-system.cpu.num_int_alu_accesses 4517 #
Number of integer alu accesses
-system.cpu.num_int_insts 4517 #
number of integer instructions
-system.cpu.num_int_register_reads 10620 #
number of times the integer registers were read
-system.cpu.num_int_register_writes 4859 #
number of times the integer registers were written
-system.cpu.num_load_insts 724 #
Number of load instructions
-system.cpu.num_mem_refs 1402 #
number of memory refs
-system.cpu.num_store_insts 678 #
Number of store instructions
-system.cpu.workload.num_syscalls 11 #
Number of system calls
+system.cpu.num_busy_cycles 5403 #
Number of busy cycles
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
---------- End Simulation Statistics ----------
diff -r 30daf1dd5c91 -r ce61b7a13407
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt Wed Jun
08 11:58:09 2011 -0500
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt Fri Jun
10 03:45:24 2011 -0400
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 87677 #
Simulator instruction rate (inst/s)
-host_mem_usage 213680 #
Number of bytes of host memory used
-host_seconds 0.06 #
Real time elapsed on the host
-host_tick_rate 4150530 #
Simulator tick rate (ticks/s)
-sim_freq 1000000000 #
Frequency of simulated ticks
-sim_insts 5340 #
Number of instructions simulated
sim_seconds 0.000253 #
Number of seconds simulated
sim_ticks 253364 #
Number of ticks simulated
-system.cpu.idle_fraction 0 #
Percentage of idle cycles
-system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+sim_freq 1000000000 #
Frequency of simulated ticks
+host_inst_rate 54602 #
Simulator instruction rate (inst/s)
+host_tick_rate 2590295 #
Simulator tick rate (ticks/s)
+host_mem_usage 234524 #
Number of bytes of host memory used
+host_seconds 0.10 #
Real time elapsed on the host
+sim_insts 5340 #
Number of instructions simulated
+system.cpu.workload.num_syscalls 11 #
Number of system calls
system.cpu.numCycles 253364 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
-system.cpu.num_busy_cycles 253364 #
Number of busy cycles
-system.cpu.num_conditional_control_insts 0 #
number of instructions that are conditional controls
+system.cpu.num_insts 5340 #
Number of instructions executed
+system.cpu.num_int_alu_accesses 4517 #
Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 #
Number of float alu accesses
+system.cpu.num_func_calls 146 #
number of times a function call or return occured
+system.cpu.num_conditional_control_insts 774 #
number of instructions that are conditional controls
+system.cpu.num_int_insts 4517 #
number of integer instructions
system.cpu.num_fp_insts 0 #
number of float instructions
+system.cpu.num_int_register_reads 10620 #
number of times the integer registers were read
+system.cpu.num_int_register_writes 4858 #
number of times the integer registers were written
system.cpu.num_fp_register_reads 0 #
number of times the floating registers were read
system.cpu.num_fp_register_writes 0 #
number of times the floating registers were written
-system.cpu.num_func_calls 0 #
number of times a function call or return occured
+system.cpu.num_mem_refs 1402 #
number of memory refs
+system.cpu.num_load_insts 724 #
Number of load instructions
+system.cpu.num_store_insts 678 #
Number of store instructions
system.cpu.num_idle_cycles 0 #
Number of idle cycles
-system.cpu.num_insts 5340 #
Number of instructions executed
-system.cpu.num_int_alu_accesses 4517 #
Number of integer alu accesses
-system.cpu.num_int_insts 4517 #
number of integer instructions
-system.cpu.num_int_register_reads 10620 #
number of times the integer registers were read
-system.cpu.num_int_register_writes 4858 #
number of times the integer registers were written
-system.cpu.num_load_insts 724 #
Number of load instructions
-system.cpu.num_mem_refs 1402 #
number of memory refs
-system.cpu.num_store_insts 678 #
Number of store instructions
-system.cpu.workload.num_syscalls 11 #
Number of system calls
+system.cpu.num_busy_cycles 253364 #
Number of busy cycles
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
---------- End Simulation Statistics ----------
diff -r 30daf1dd5c91 -r ce61b7a13407
tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt Wed Jun
08 11:58:09 2011 -0500
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt Fri Jun
10 03:45:24 2011 -0400
@@ -1,218 +1,218 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 539149 #
Simulator instruction rate (inst/s)
-host_mem_usage 203248 #
Number of bytes of host memory used
-host_seconds 0.01 #
Real time elapsed on the host
-host_tick_rate 2800713812 #
Simulator tick rate (ticks/s)
-sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 5340 #
Number of instructions simulated
sim_seconds 0.000028 #
Number of seconds simulated
sim_ticks 28206000 #
Number of ticks simulated
+sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 272526 #
Simulator instruction rate (inst/s)
+host_tick_rate 1437682899 #
Simulator tick rate (ticks/s)
+host_mem_usage 225224 #
Number of bytes of host memory used
+host_seconds 0.02 #
Real time elapsed on the host
+sim_insts 5340 #
Number of instructions simulated
+system.cpu.workload.num_syscalls 11 #
Number of system calls
+system.cpu.numCycles 56412 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
+system.cpu.num_insts 5340 #
Number of instructions executed
+system.cpu.num_int_alu_accesses 4517 #
Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 0 #
Number of float alu accesses
+system.cpu.num_func_calls 146 #
number of times a function call or return occured
+system.cpu.num_conditional_control_insts 774 #
number of instructions that are conditional controls
+system.cpu.num_int_insts 4517 #
number of integer instructions
+system.cpu.num_fp_insts 0 #
number of float instructions
+system.cpu.num_int_register_reads 10620 #
number of times the integer registers were read
+system.cpu.num_int_register_writes 4858 #
number of times the integer registers were written
+system.cpu.num_fp_register_reads 0 #
number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 #
number of times the floating registers were written
+system.cpu.num_mem_refs 1402 #
number of memory refs
+system.cpu.num_load_insts 724 #
Number of load instructions
+system.cpu.num_store_insts 678 #
Number of store instructions
+system.cpu.num_idle_cycles 0 #
Number of idle cycles
+system.cpu.num_busy_cycles 56412 #
Number of busy cycles
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
+system.cpu.icache.replacements 0 #
number of replacements
+system.cpu.icache.tagsinuse 116.975932 #
Cycle average of tags in use
+system.cpu.icache.total_refs 5127 #
Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 257 #
Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 19.949416 #
Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 116.975932 #
Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.057117 #
Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 5127 #
number of ReadReq hits
+system.cpu.icache.demand_hits 5127 #
number of demand (read+write) hits
+system.cpu.icache.overall_hits 5127 #
number of overall hits
+system.cpu.icache.ReadReq_misses 257 #
number of ReadReq misses
+system.cpu.icache.demand_misses 257 #
number of demand (read+write) misses
+system.cpu.icache.overall_misses 257 #
number of overall misses
+system.cpu.icache.ReadReq_miss_latency 14308000 #
number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 14308000 #
number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 14308000 #
number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 5384 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 5384 #
number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 5384 #
number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.047734 #
miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.047734 #
miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.047734 #
miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55673.151751
# average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55673.151751 #
average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55673.151751
# average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 #
number of fast writes performed
+system.cpu.icache.cache_copies 0 #
number of cache copies performed
+system.cpu.icache.writebacks 0 #
number of writebacks
+system.cpu.icache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 #
number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 257 #
number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 257 #
number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 257 #
number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 13537000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 13537000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 13537000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.047734 #
mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.047734 #
mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751
# average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751
# average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751
# average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 #
number of replacements
+system.cpu.dcache.tagsinuse 82.065697 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 1254 #
Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 #
Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 9.288889 #
Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 82.065697 #
Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.020036 #
Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 662 #
number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 592 #
number of WriteReq hits
+system.cpu.dcache.demand_hits 1254 #
number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1254 #
number of overall hits
+system.cpu.dcache.ReadReq_misses 54 #
number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 81 #
number of WriteReq misses
+system.cpu.dcache.demand_misses 135 #
number of demand (read+write) misses
+system.cpu.dcache.overall_misses 135 #
number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 2982000 #
number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 4536000 #
number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7518000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7518000 #
number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 716 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 673 #
number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 1389 #
number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 1389 #
number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.075419 #
miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.120357 #
miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.097192 #
miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.097192 #
miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 662 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2982000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.075419 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 54 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2820000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 54 #
number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 673 #
number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 592 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4536000 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.120357 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 81 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4293000
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 81 #
number of WriteReq MSHR misses
+system.cpu.dcache.demand_avg_miss_latency 55688.888889 #
average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 55688.888889
# average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 9.288889 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 1389 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55688.888889 #
average overall miss latency
+system.cpu.dcache.writebacks 0 #
number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 54 #
number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 81 #
number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 135 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 135 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2820000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 4293000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7113000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7113000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.097192 #
mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.097192 #
mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222
# average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000
# average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 1254 #
number of demand (read+write) hits
_______________________________________________
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev
