On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does vary in each iteration, sometimes it is above 100. So I think it should be the physical register value. If my understanding is correct, the physical register should be set during the IEW stage before the instruction is commited or squashed at the last stage. Otherwise out-of-order execution wouldn't be possible. So in the end I am searching the point at which the physical register is set and marked as ready for subsequent instruction, which depend on this specific register.
Yes, it makes sense that it is a physical register. For arithmetic, register to register move, etc., it would be written in IEW. But for loads, it cannot be written until LSQ processing, which is later in the pipeline. I believe there is a notion of the register being *ready*, and it will be marked ready when it is written. Likewise, once all of an instruction's input registers are ready, that instruction may be executed (the instruction itself becomes ready). You can look for the 'writeback' function in lsq_unit.cc. It clearly has some relationship to IEW, but it explicitly calls completeAcc, which does the actual write into the register. The specific code for that came from the instruction's template. This is necessarily so - consider the difference between loading a byte (say) vs a word, and sign- vs zero-extended values. Regards - EM _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
