On Thu, 26 May 2011, Daniel Chang wrote:
I am trying to produce DRAMSim compatible memory traces for applications I normally run on M5 and am having some difficulty obtaining accurate cache miss information. Specifically DRAMSim needs three bits of information: the cycle at which the memory request is sent to the memory controller, the address or the request and the type of request (Read/Write).I've been able to get a semi-working solution where I print out the address/cycle/type information for *every* data and instruction cache request (i.e. missCycle, req.addr and req.type) and then also print out any requests that stall beyond 20 cycles. I then do pattern matching (in Perl) to match those stalled requests with a data/instruction cache cache request from earlier so I can obtain the address/cycle/type information that went to the memory controller. This is a crude solution and I think it will work, however I have a feeling there has to be a more elegant solution. Specifically one that doesn't generate huge text files. With that said, what files should I be looking at to get the last cache miss information? I've looked at the missqueue.cc and other files in the "miss" folder, but none of the functions seem to have the information I require (address/cycle/type sent to controller). Worst case, I can use my current solution, but I figured I'd ask since I'm sure there is a file and function that already has this information and would require me not making huge text files that contain *every* cache request (hit or miss) :). Thanks! -Daniel
Which memory system are you making use of? -- Nilay
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