Do you run into the problem in 2 on more than one CPU model? Does an
unmodified version of gem5 from the most recent version of the
development repository hit the same problem? If so, please send me
your binary directly (to spare everyone's inboxes) and I'll take a
look. What instruction is it attempting to fetch the microop from?
Gabe
Quoting Newsha Ardalani <new...@cs.wisc.edu>:
Hey all,
I have developed a cache coherency protocol for a course project and
I like to test its capability:
1. I have written a very simple multithreaded program that has the
features my protocol best fits to and cross-compiled it for alpha
architecture but when I ran it (using se.py) it gives some error
that some sys calls are not implemented. I commented all those sys
calls as suggested but I faced with a bad memory access that I guess
it was caused because I commented those system calls. Do you know
which files should I change if I finally decide to implement some of
those unimplemented syscalls?
2. Then I decided to compile the M5 for x86 architecture and passed
the files simply compiled on my linux, but there were again some
assertion error, Do you know what could be the reason? I debugged it
and microPC and numMicroops are both 1.
m5.debug: build/X86_SE/arch/x86/insts/macroop.hh:79: virtual
StaticInstPtr X86ISA::MacroopBase::fetchMicroop(MicroPC) const:
Assertion `microPC < numMicroops' failed.
3. Now I'm thinking of changing the ruby_random_tester, my problem
with random_tester is that the values stored to memory locations
never return to their previous value and so I can not check the
corner cases of my protocol. I like to change the values stored to
memory to force the characteristics I like. Do you know what files I
should change? or more precisely, which file generates the random
loads and stores and their random value?
Thank you,
--newsha
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