On Mon, 2024-03-25 at 23:35 +0100, Tomas Volf wrote: > I (think I) can just swap the order and do `CC=gcc make' in order to > work around the issue (is that correct assumption?), but would like > to understand why it behaves like this.
Dmitry explained that in versions of GNU Make prior to 4.4, none of the extra variables in the makefile were passed to the $(shell ...) function. Using "CC=cc make" may work, or not, depending on your makefile. Variables assigned in the makefile take precedence over variables inherited from the environment, while variables added to the command line as arguments take precedence over variables defined in the makefile. So if your makefile says: CC = gcc then running "make CC=cc" WILL override it, but "CC=cc make" WILL NOT override it. If your makefile says: CC ?= gcc then both will work. A more flexible, although slightly annoying, option is to set the variable(s) in the $(shell ...) code directly: yyy = $(shell foo='$(foo)' env | grep ^foo=) If there are a lot of them you can of course put the variables you care about in a variable then expand them, like: VARS := foo CC ENVSET = $(foreach V,$(VARS),$V='$($V)') yyy = $(shell $(ENVSET) env | grep ^foo=) (I should point out that this change in GNU Make 4.4 has the potential to cause your makefile to take exponentially more time to run if you are not careful; in particular you really want to be using simple expansion (:=) with the $(shell ...) function).
