In <4e20f40d.2050...@phoenixsoftware.com>, on 07/15/2011
at 07:14 PM, Edward Jaffe <edja...@phoenixsoftware.com> said:
>There is no way the processor can know in advance which bits will be
>on in a branch target register, so its seems likely that the
>pipeline must be flushed when 'surprise' AMODE switching occurs for
>pointer-defined linkage.
Why would a branch with AMODE switching require more pipeline flushing
than a branch without?
--
Shmuel (Seymour J.) Metz, SysProg and JOAT
ISO position; see <http://patriot.net/~shmuel/resume/brief.html>
We don't care. We don't have to care, we're Congress.
(S877: The Shut up and Eat Your spam act of 2003)
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