The following message is a courtesy copy of an article that has been posted to alt.folklore.computers,bit.listserv.ibm-main as well.
[EMAIL PROTECTED] (Rob Warnock) writes: > Even the very first Lisp (1958) had a compiler (by 1962) to native > machine code, as did almost every one which followed (except a few > toy systems). The notion that "Lisp is (only) interpreted" is an > urban myth that seemingly won't die, possibly because almost every > Lisp system with a compiler *also* contains an interactive interpreter, > and permits free *mixing* of compiled and interpreted code in the > same program: old email (in these posts) referencing lisp machine people asking about being able to get a 801/risc processor (for the machine) and being offered an 8100 instead (some flavor of uc.5 processor i believe). http://www.garlic.com/~lynn/2003e.html#65 801 (was Re: Reviving Multics http://www.garlic.com/~lynn/2006c.html#3 Architectural support for programming languages http://www.garlic.com/~lynn/2006o.html#45 "25th Anniversary of the Personal Computer" http://www.garlic.com/~lynn/2006t.html#9 32 or even 64 registers for x86-64? for further trivia ... Evans eventually did ask my wife to do audit of 8100 ... which did result in it getting can'ed. this is somewhat related to whether the 801/risc is executing microcode and emulating a different architecture (as in the case of lisp machine) or is directly executing "native" code (for purest, in both cases it is executing "native" code). this is also related to recent post about directly execution of 370, emulating 370 in m'code and/or offloading directly to native code http://www.garlic.com/~lynn/2008k.html#21 IBM's 2Q2008 Earnings the above mentions trying to cram up to 80 (arbitrary mix of 370 and 801) processors in single rack (circa 1985) as well as (circa fall 1991) *medusa* getting 32 processors in single rack (both cases possibly having arbitrary number of racks). in both cases, a major gating factor was getting the heat out of the racks. the question of directly, emulated, and/or (offloaded) native, I had (also) looked at a decade earlier (mid-70s) with both virgal/tully (i.e. 138/148) ECPS effort ... old reference http://www.garlic.com/~lynn/94.html#21 370 ECPS VM micrcode assist and VAMPS multiprocessor ... lots of past posts http://www.garlic.com/~lynn/subtopic.html#bounce In the 138/148 (which evolved into 4331/4341 and then 4361/4381) was m'code 370 emulation that avg. about 10 native instructions to emulated 370 instructions. A major piece of ECPS was to select 6k bytes of the highest used kernel instructions and do an (approx) 1-for-1 translation into native microcdoe (getting 10-to-1 performance improvement) ... the earlier post gives kernel path analysis used to select the 6k bytes moved into microcode. It wasn't directly offload in the sense that function executed on different processor. The same time as ECPS, I also did VAMPS (which never was announced) multiprocessor operation. The native machine had a nine-position microprocessor memory bus. Delivered to customers it was a single 370 processor with integrated channels and controllers. Underneath there werer several identical microprocessors, one running 370 microcode and others executing microcode loads for various integrated control unit functions. VAMPS effort was to do the hardware and software necessary to support up to five of the microprocessors executing the 370 microprocessor load. I had done a higher-level multiprocessor function architecture (additional function with some similarities to the later intel i432). I had also done a higher level architecture for I/O that allowed *offloading* lots of queueing and interrupt processing into the disk controller (*IOP*), somewhat akin to later 370/XA. In the mainframe world ... an example of "offloading" later in the 70s, was the 303x channel director. The 370/158 had microcode for both 370 emulation and integrated channels (sharing the same microprocessr). For 303x, they split off the 370/158 integrated channel microcode into a separate dedicated box (channel director). 370/158 turned into a 3031 with two 370/158 microprocessors (instead of just one); one with just the 370/158 370 emulation microcde and the second with just the integrated channel microcode. A 370/168 became 3032 with one to three channel directors. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
