On Wed, Mar 13, 2024 at 09:19:51PM +0100, Andi Shyti wrote:
> Enable only one CCS engine by default with all the compute sices
> allocated to it.
>
> While generating the list of UABI engines to be exposed to the
> user, exclude any additional CCS engines beyond the first
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti <andi.sh...@linux.intel.com>
> Cc: Chris Wilson <chris.p.wil...@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: <sta...@vger.kernel.org> # v6.2+
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 39 +++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 13 +++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++
> 5 files changed, 65 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3ef6ed41e62b..a6885a1d41a1 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -118,6 +118,7 @@ gt-y += \
> gt/intel_ggtt_fencing.o \
> gt/intel_gt.o \
> gt/intel_gt_buffer_pool.o \
> + gt/intel_gt_ccs_mode.o \
> gt/intel_gt_clock_utils.o \
> gt/intel_gt_debugfs.o \
> gt/intel_gt_engines_debugfs.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> new file mode 100644
> index 000000000000..044219c5960a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_gt.h"
> +#include "intel_gt_ccs_mode.h"
> +#include "intel_gt_regs.h"
> +
> +void intel_gt_apply_ccs_mode(struct intel_gt *gt)
> +{
> + int cslice;
> + u32 mode = 0;
> + int first_ccs = __ffs(CCS_MASK(gt));
> +
> + if (!IS_DG2(gt->i915))
> + return;
> +
> + /* Build the value for the fixed CCS load balancing */
> + for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
> + if (CCS_MASK(gt) & BIT(cslice))
> + /*
> + * If available, assign the cslice
> + * to the first available engine...
> + */
> + mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
> +
> + else
> + /*
> + * ... otherwise, mark the cslice as
> + * unavailable if no CCS dispatches here
> + */
> + mode |= XEHP_CCS_MODE_CSLICE(cslice,
> + XEHP_CCS_MODE_CSLICE_MASK);
> + }
> +
> + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
> b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
> new file mode 100644
> index 000000000000..9e5549caeb26
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_GT_CCS_MODE_H__
> +#define __INTEL_GT_CCS_MODE_H__
> +
> +struct intel_gt;
> +
> +void intel_gt_apply_ccs_mode(struct intel_gt *gt);
> +
> +#endif /* __INTEL_GT_CCS_MODE_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 31b102604e3d..743fe3566722 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1480,6 +1480,11 @@
> #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
> #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
>
> +#define XEHP_CCS_MODE _MMIO(0x14804)
> +#define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 +
> rsvd */
> +#define XEHP_CCS_MODE_CSLICE_WIDTH ilog2(XEHP_CCS_MODE_CSLICE_MASK
> + 1)
> +#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice *
> XEHP_CCS_MODE_CSLICE_WIDTH))
> +
> #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
> #define CHV_FGT_DISABLE_SS0 (1 << 10)
> #define CHV_FGT_DISABLE_SS1 (1 << 11)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9963e5725ae5..8188c9f0b5ce 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -10,6 +10,7 @@
> #include "intel_engine_regs.h"
> #include "intel_gpu_commands.h"
> #include "intel_gt.h"
> +#include "intel_gt_ccs_mode.h"
> #include "intel_gt_mcr.h"
> #include "intel_gt_print.h"
> #include "intel_gt_regs.h"
> @@ -2869,6 +2870,12 @@ static void ccs_engine_wa_mode(struct intel_engine_cs
> *engine, struct i915_wa_li
> * made to completely disable automatic CCS load balancing.
> */
> wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> +
> + /*
> + * After having disabled automatic load balancing we need to
> + * assign all slices to a single CCS. We will call it CCS mode 1
> + */
> + intel_gt_apply_ccs_mode(gt);
> }
>
> /*
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
