Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_RES_1_IVB register macro.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c337e0597541..45abbc169bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -356,7 +356,7 @@ static void hsw_pipe_crc_irq_handler(struct 
drm_i915_private *dev_priv,
                                     enum pipe pipe)
 {
        display_pipe_crc_irq_handler(dev_priv, pipe,
-                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_1_IVB(pipe)),
+                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
                                     0, 0, 0, 0);
 }
 
@@ -364,7 +364,7 @@ static void ivb_pipe_crc_irq_handler(struct 
drm_i915_private *dev_priv,
                                     enum pipe pipe)
 {
        display_pipe_crc_irq_handler(dev_priv, pipe,
-                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_1_IVB(pipe)),
+                                    intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_1_IVB(dev_priv, pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_2_IVB(pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_3_IVB(pipe)),
                                     intel_uncore_read(&dev_priv->uncore, 
PIPE_CRC_RES_4_IVB(pipe)),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c8a9c5ccd4f..cabc938843b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1650,7 +1650,7 @@
 #define _PIPE_CRC_RES_5_B_IVB          0x61074
 
 #define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_CTL_A)
-#define PIPE_CRC_RES_1_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_1_A_IVB)
+#define PIPE_CRC_RES_1_IVB(dev_priv, pipe)     _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_1_A_IVB)
 #define PIPE_CRC_RES_2_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_2_A_IVB)
 #define PIPE_CRC_RES_3_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_3_A_IVB)
 #define PIPE_CRC_RES_4_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, 
_PIPE_CRC_RES_4_A_IVB)
-- 
2.39.2

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