When L2 exits to L1, segment infomations of L1 are not set correctly.
According to Intel SDM 27.5.2(Loading Host Segment and Descriptor
Table Registers), segment base/limit/access right of L1 should be
set to some designed value when L2 exits to L1. This patch fixes
this.
Signed-off-by: Arthur Chunqi Li <yzt...@gmail.com>
---
arch/x86/kvm/vmx.c | 58 +++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 48 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 064d0be..0ea9614 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -7948,6 +7948,8 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct
vmcs12 *vmcs12)
static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
struct vmcs12 *vmcs12)
{
+ struct kvm_segment seg_cs, seg_ds, seg_tr;
+
if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
vcpu->arch.efer = vmcs12->host_ia32_efer;
else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
@@ -8001,16 +8003,6 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
- vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
- vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
- vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
- vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
- vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
- vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
- vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
- vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
- vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
- vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
@@ -8018,6 +8010,52 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
vmcs12->host_ia32_perf_global_ctrl);
+ /* Set L1 segment info according to Intel SDM
+ 27.5.2 Loading Host Segment and Descriptor-Table Registers */
+ memset(&seg_cs, 0, sizeof(struct kvm_segment));
+ memset(&seg_ds, 0, sizeof(struct kvm_segment));
+ memset(&seg_tr, 0, sizeof(struct kvm_segment));
+ seg_cs.base = 0;
+ seg_cs.limit = 0xFFFFFFFF;
+ seg_cs.selector = vmcs12->host_cs_selector;
+ seg_cs.type = AR_TYPE_CODE_MASK | AR_TYPE_READABLE_MASK
+ | AR_TYPE_ACCESSES_MASK;
+ seg_cs.present = 1;
+ if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
+ seg_cs.l = 1;
+ else
+ seg_cs.db = 1;
+ seg_cs.s = 1;
+ seg_cs.g = 1;
+ vmx_set_segment(vcpu, &seg_cs, VCPU_SREG_CS);
+ seg_ds.base = 0;
+ seg_ds.limit = 0xFFFFFFFF;
+ seg_ds.type = AR_TYPE_READABLE_MASK | AR_TYPE_ACCESSES_MASK;
+ seg_ds.present = 1;
+ seg_ds.s = 1;
+ seg_ds.db = 1;
+ seg_ds.g = 1;
+ seg_ds.selector = vmcs12->host_ds_selector;
+ vmx_set_segment(vcpu, &seg_ds, VCPU_SREG_DS);
+ seg_ds.selector = vmcs12->host_es_selector;
+ vmx_set_segment(vcpu, &seg_ds, VCPU_SREG_ES);
+ seg_ds.selector = vmcs12->host_ss_selector;
+ vmx_set_segment(vcpu, &seg_ds, VCPU_SREG_SS);
+ seg_ds.selector = vmcs12->host_fs_selector;
+ seg_ds.base = vmcs12->host_fs_base;
+ vmx_set_segment(vcpu, &seg_ds, VCPU_SREG_FS);
+ seg_ds.selector = vmcs12->host_gs_selector;
+ seg_ds.base = vmcs12->host_gs_base;
+ vmx_set_segment(vcpu, &seg_ds, VCPU_SREG_GS);
+ seg_tr.base = vmcs12->host_tr_base;
+ seg_tr.limit = 0x67;
+ seg_tr.selector = vmcs12->host_tr_selector;
+ seg_tr.type = AR_TYPE_CODE_MASK | AR_TYPE_READABLE_MASK
+ | AR_TYPE_ACCESSES_MASK;
+ seg_tr.present = 1;
+ vmx_set_segment(vcpu, &seg_tr, VCPU_SREG_TR);
+
+
kvm_set_dr(vcpu, 7, 0x400);
vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
}
--
1.7.9.5
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