e9hack wrote:
> Trent Piepho wrote:
> > 
> > Does the stv0297 require that no other i2c traffic, to a different device,
> > appear between the write and the read?  Something like:
> > 
> > S stv_addr_W A reg_addr A P
> > S tuner_addr_W A tuner_data1 A tuner_data2 A P
> > S stv_addr_R A reg_data NA P
> > 
> > Will the i2c message to the tuner between the two parts of the stv register
> > reading sequence be a problem?
> 
> The tuner may be a problem, because the stv0297 is the gate for the tuner 
> i2c-bus.

Correct. Since the I2C gate closes after the following stop condition,
we have a problem, if another I2C transfer happens between gate open and
PLL access:

(1) S stv_addr_W A ...open_gate... P
(2) S eeprom_addr_W A reg_addr A Sr eeprom_addr_R A reg_data NA P
(3) S pll_addr_W A ...pll_data... P

will not work because the I2C gate closes after (2)!

> Reading from eeprom does work: 
> 
> S stv_addr_W A reg_addr A P
> S eeprom_addr_W A reg_addr A Sr eeprom_addr_R A reg_data NA P
> S stv_addr_R A reg_data NA P

Could you please test whether this works:
S stv_addr_W A reg_addr A Sr stv_addr_R A reg_data NA P

CU
Oliver

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