On Wed, 21 Feb 2007 15:56:28 -0700 "Fajun Chen" <[EMAIL PROTECTED]> wrote:
> Hi Folks, > > I've noticed the following code in both pata_sil680.c and IDE code siimage.c > /* FIXME: double check */ > pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); > I was unable to find the recommended setting in Sil680 document. Could > someone explain the rational behind the code above? Does it need to be > adjusted on different processors for PCI read/write performance? The code is inherited from the original bits by Andre Hedrick who had access to the chip errata documents, which afaik have never been published. - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
