> > A thing that crossed my mind was a timing issue. Perhaps the dmaing of < > > 60 bytes is that > > fast that the interrupt that causes it is not yet handled correctly. But > > this is just a very wild guess. > > I don't think that can happen. Controllers are required to queue > interrupt till FIFO is flushed. Can you post dmesg after such errors?
Random finger in the air guess - the FIFO on the SIL DMA engine is 64 bytes long ? Perhaps this is something Jeff can query with his contacts at Silicon Image ? Alan - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
