Hello.
Alan Cox wrote:
hpt37x: Bus clock 66 MHz, using DPLL.
Oh?! hpt366.c detected 33 MHz... :-O
Interesting as it should be using the same algorithm as hpt366 now.
Actually not: when pata_hpt37x decides to use DPLL, it reports the chosen
*DPLL* clock instead of the PCI clock. The question is why it chose 66 MHz on
HPT374... Looks like it's because of this wrong mask which should be 0xc0:
dpll = 2;
if (port->udma_mask & 0xE0)
dpll = 3;
ACPI: PCI Interrupt 0000:00:0d.0[A] -> GSI 16 (level, low) -> IRQ 17
scsi2: pata_hpt37x
scsi3: pata_hpt37x
ata3: PATA max UDMA/100 cmd 0x0001efa0 ctl 0x0001ef9e bmdma 0x0001ec00 irq 17
ata4: PATA max UDMA/100 cmd 0x0001ef90 ctl 0x0001ef9a bmdma 0x0001ec00 irq 17
and it also knows about the bridge knobbling stuff. Most curious
Not curious at all now. ;-) The former HPT374 clocking fix just remained
ineffective.
MBR, Sergei
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