Minor cleanup to remove the unneeded rmb()s per Jeff's advice. Also removed the
pll_clock < 0 check since pll_clock now guaranteed to be >= 0 after Mikael's
patch.
Signed-off-by: Albert Lee <[EMAIL PROTECTED]>
---
Tested ok on both x86 and ppc64, together with Mikael's patch.
diff -Nrup 01_mikael/drivers/ata/pata_pdc2027x.c
02_pdc_pll_fix2/drivers/ata/pata_pdc2027x.c
--- 01_mikael/drivers/ata/pata_pdc2027x.c 2007-08-20 10:43:38.000000000
+0800
+++ 02_pdc_pll_fix2/drivers/ata/pata_pdc2027x.c 2007-08-20 10:48:22.000000000
+0800
@@ -565,12 +565,10 @@ static long pdc_read_counter(struct ata_
retry:
bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
- rmb();
/* Read the counter values again for verification */
bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
- rmb();
counter = (bccrh << 15) | bccrl;
@@ -745,9 +743,6 @@ static int pdc_hardware_init(struct ata_
*/
pll_clock = pdc_detect_pll_input_clock(host);
- if (pll_clock < 0) /* counter overflow? Try again. */
- pll_clock = pdc_detect_pll_input_clock(host);
-
dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n",
pll_clock/1000);
/* Adjust PLL control register */
-
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