(I actually wrote this a few days ago, but the list moderator
seems to be sitting on my email, so I've subscribed since I think
there's a few people on this list who are insterested...
You'll have to CC any replies to me at [EMAIL PROTECTED]
since I'll be unsubscribing again.)
I've been playing with my new laptop, and this is what I
have: (Toshiba Satellite Pro 4600)
The chip is an SMSC LPC47N227 which is an integrated SuperIO
chip including an SMSC IrCC 2.0 chip. The codename of the
LPC47N227 is "Kona". (Which is what Toshiba referred to
the IR chip as.)
For some reason, the laptop's bootup configuration has the
serial port enabled, but the IR port is disabled, as was
observed by someone on this email list in June.
I got these settings from http://www.roe.ac.uk/~hme/tosh4600/
I/O range 02F8-02FF
IRQ 10
I/O range 0130-0137
DMA 01
To enable the port, here's what needs to be done:
(This is using the LPC47N227's configuration registers,
living at 0x2E. See the datasheet on SMSC's website)
Write 0xBE to CR25 (Sets UART2 base addy to 0x2F8)
Set the low four bits of CR28 to 0xA (Sets UART2 IRQ to 10)
Write 0x26 to CR2B (Sets the FIR base addy to 0x130)
Write 0x01 to CR2C (Sets FIR DMA channel to 1)
Set bits 5,4,3 of CR0C to 001. (Sets UART2 mode to IrDA) ?
Set bit 5 of CR07. (Enables Autopowerdown mode of UART 2) ?
Set bit 7 of CR02. (Powers up UART2)
Set bit 8 of CR00. (Indicate valid configuration)
(The '?' mean that line may not be needed. I don't know
which of those are needed, in fact. :-)
This configures the SMSC chip, but the LPC controller on
the PCI bus at 00:1f.0 still doesn't know about the newly
enabled ports. So we do the following:
(This comes from the 82801BAM datasheet on intel's website)
(This part is done in the PCI configuration space of the
LPC Interface controller (8086:244c) at 00:1f.0)
Set bits 6:4 in the 8-bit value at 0xE0 to 001
(Sets the decode range for COMB on the LPC controller)
Set bit 1 in the 16-bit value at 0xE6 to 1
(Enable COMB mapping from the PCI bus to the LPC bus)
Set bits 3:2 in the 16-bit value at 0x90 to 11
(Mark DMA 1 as an LPC DMA)
Set 16-bit value at 0xEc to 0x131
0000 0001 0011 ---- Base address (0x130)
---- ---- ---- ---1 Enable Decoding
(This is a general decode range for the LPC controller
and in fact maps 0x130 - 0x13f onto the LPC bus behind
the LPC controller. But that's as fine-grained as I
can get. The other choice is a 128-byte range. :-)
Now the smc-ircc kernel module will load quite happily,
and setserial can auto-config the IRQ for tts/1 (once I've
created the dev-node, since I'm on devfs)
However, I don't seem to be able to see anything with
irdadump or in /proc/net/irda/discovery. I've only got a
Nokia 8250 and a HP Jornada 548 to play with, so I dunno
if I can expect to see anything. I'm not exactly sure how
to use irattach and the like either.
I've attached the two programs I wrote to do these changes.
The PCI config space stuff uses the lib directory from
pci-utils. You'll want to edit the makefile. :-)
There's also testport.c which just dumps all the config
registers from the SMSC chip, and the queries the 3rd
register bank on the IrCC's FIR port if it's in the CR
regs.
(It's worth pointing out that setsmc's changes survive a
reboot, but setpci's don't. So I can't make linux find the
serial port on reset, and have to do the makenod myself.
Maybe this should go in the toshiba kernel module....)
--
===========================================================
Paul "TBBle" Hampson, MCSE
4th year B.SEng student, ANU (Student Number s3160518)
The Boss, Bubblesworth Pty Ltd (ABN: 51 095 284 361)
[EMAIL PROTECTED]
Of course Pacman didn't influence us as kids. If it did,
we'd be running around in darkened rooms, popping pills and
listening to repetitive music.
This email is licensed to the recipient for non-commercial
use, duplication and distribution.
===========================================================
setpci: setpci.c
gcc -g -O2 -o setpci setpci.c -lpci -I../pci/pciutils-2.1.8/lib
-L../pci/pciutils-2.1.8/lib
setsmc: setsmc.c
gcc -g -O2 -o setsmc setsmc.c
testport: testport.c
gcc -g -O2 -o testport testport.c
#include <stdio.h>
#include <asm/io.h>
#include "pci.h"
#define BASE 0x2e
int main()
{
struct pci_access *acc;
struct pci_dev *dev;
byte onebyte;
word twobyte;
acc = pci_alloc();
pci_init(acc);
dev = pci_get_dev(acc, 0x00, 0x1f, 0x00);
onebyte = pci_read_byte(dev, 0xe0);
onebyte &= 0x8f;
onebyte |= 0x10;
pci_write_byte(dev, 0xe0, onebyte);
twobyte = pci_read_word(dev, 0xe6);
twobyte &= 0xfffd;
twobyte |= 0x0002;
pci_write_word(dev, 0xe6, twobyte);
twobyte = pci_read_word(dev, 0x90);
twobyte &= 0xfff3;
twobyte |= 0x000c;
pci_write_word(dev, 0x90, twobyte);
pci_write_word(dev, 0xec, 0x131);
pci_free_dev(dev);
pci_cleanup(acc);
}
#include <stdio.h>
#include <asm/io.h>
#define BASE 0x2e
int main()
{
int i;
ioperm(BASE, 2, 1);
outb(0x55, BASE);
outb(0x0d, BASE);
if (inb(BASE+1) == 0x5a)
{
outb(0x25, BASE);
outb(0xBE, BASE+1);
outb(0x28, BASE);
i = inb(BASE+1);
outb((i & 0xf0) | 0x0a, BASE+1);
outb(0x2B, BASE);
outb(0x26, BASE+1);
outb(0x2C, BASE);
outb(0x01, BASE+1);
outb(0x0C, BASE);
i = inb(BASE+1);
outb((i & 0xC7) | 0x08, BASE+1);
outb(0x07, BASE);
i = inb(BASE+1);
outb(i | 0x20, BASE+1);
outb(0x02, BASE);
i = inb(BASE+1);
outb(i | 0x80, BASE+1);
outb(0x00, BASE);
i = inb(BASE + 1);
outb(i | 0x80, BASE + 1);
outb(0xaa, BASE);
}
}
#include <stdio.h>
#include <asm/io.h>
#define BASE 0x2e
int main()
{
int i;
int fir_base;
ioperm(BASE, 2, 1);
outb(0x55, BASE);
outb(0x0d, BASE);
if (inb(BASE+1) == 0x5a)
{
for (i=0; i<=0x39; i++)
{
outb(i, BASE);
printf("CR%02x: %02x\n", i, inb(BASE+1));
}
}
outb(0x2B, BASE);
fir_base = inb(BASE+1) << 3;
outb(0xaa, BASE);
printf("FIR Base port: %04x\n", fir_base);
if (fir_base)
{
ioperm(fir_base, 8, 1);
i = inb(fir_base + 7);
outb((i & 0xf8) | 0x03, fir_base);
for (i=0; i < 7; i++)
{
printf("Reg 3.%02x: %02x\n", i, inb(fir_base+i));
}
}
}
