On Wed, 10 Nov 2010, Baruch Siach wrote:

> Guennadi Liakhovetski <g.liakhovetski <at> gmx.de> writes:
> 
> > On Wed, 27 Oct 2010, Baruch Siach wrote:
> > > When SOCAM_PCLK_SAMPLE_FALLING, just leave CSICR1_REDGE unset, 
> > > otherwise we get
> > > the inverted behaviour.
> > Seems logical to me, that if this is true, then you need the inverse:
> > 
> >     if (!(common_flags & SOCAM_PCLK_SAMPLE_FALLING))
> >             csicr1 |= CSICR1_INV_PCLK;
> 
> No. Doing so you'll get the inverted behaviour of SAMPLE_RISING. When
> common_flags have SAMPLE_RISING set and SAMPLE_FALLING unset you get
> CSICR1_REDGE set, which triggers on the rising edge, and then also
> CSICR1_INV_PCLK set, which invert this. Thus you get the expected 
> behaviour of SAMPLE_FALLING.
> 
> Currently you get the inverted behaviour only for SAMPLE_FALLING.
> 
> IMO, we should just use CSICR1_REDGE to set the sample timing, and leave
> CSICR1_INV_PCLK alone.

Ah, right, of course, I've overlooked that CSICR1_REDGE flag. Then yes, 
your patch makes sense and should go in for 2.6.37.

Thanks
Guennadi

> 
> baruch
> 
> > >   if (common_flags & SOCAM_PCLK_SAMPLE_RISING)
> > >           csicr1 |= CSICR1_REDGE;
> > > - if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
> > > -         csicr1 |= CSICR1_INV_PCLK;
> > >   if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
> > >           csicr1 |= CSICR1_SOF_POL;
> > >   if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
> 
> 
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---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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