Remove un-necessary bit masking. Since the register are 4 byte aligned
and readl would work as is. The 'enabled' mask is already taking care
to mask for bank width.
Signed-off-by: Charulatha V <ch...@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.ka...@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilim...@ti.com>
---
drivers/gpio/gpio-omap.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 876e387..d614c6d 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -571,8 +571,6 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
enabled = _get_gpio_irqbank_mask(bank);
isr_saved = isr = __raw_readl(isr_reg) & enabled;
- if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
- isr &= 0x0000ffff;
if (bank->level_mask)
level_mask = bank->level_mask & enabled;
--
1.7.0.4
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