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Opteron has sixteen 64 bit
architectural integer registers. Not visible for the programmer are
eight more 64 bit scratch registers used to store intermediate results
for micro code routines that handle more complex x86 instructions. The
Athlon family of processors handles Register Renaming in the simplest
possible way. Which is a compliment because it often takes a lot of
smart thinking to figure out how to do things in the simplest way!
People only rarely succeed in this ...
As we said, each instruction in
flight needs a different destination register. The total number of
renamed registers must be equal or larger then the sum of all instructions-in-flight plus the architectural-registers. The maximum number of
instruction in flight is 72, add everything together then you need 96
"renamed registers". Two different structures are used to maintain
these registers. The instructions-in-flight results are maintained by
the result fields of the 72 entry Re-Order Buffer ( ROB ) and the
architectural-registers are maintained by the "Integer Future File and
Register File". ( IFFRF )
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Re-Order-Buffer
Tag definition
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wrap
bit
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Instruction In Flight Number
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re-order buffer index 0...23
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sub-index 0..2
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bit 7
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bit 6
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bit 5
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bit 4
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bit 3
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bit 2
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bit 1
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bit 0
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This configuration allows for a
very simple renaming scheme which takes -zero- cycles... Each
instruction dispatched from one of the three decode lanes gets a "Re-Order Buffer Tag" or "Instruction In Flight Tag" consisting of:
1) A sub-index 0,1 or 2 which
identifies from which of the three lanes the instruction was dispatched.
2) A value 0..23 that identifies the "cycle" in
which the instruction was dispatched. The "cycle counter" wraps to 0
after reaching 23.
3) A wrap bit. When two instructions have different
wrap bits then the cycle counter has wrapped between the dispatches.
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