[linuxkernelnewbies] XDR DRAM - Wikipedia, the free encyclopedia

[Peter Teoh]

http://en.wikipedia.org/wiki/XDR-DRAM XDR DRAM From Wikipedia, the free encyclopedia   (Redirected from XDR-DRAM) Jump to: navigation, search This article does not cite any references or sources. Please help improve this article by adding citations to reliable sources. Unverifiable material may be challenged and removed. (December 2006) DRAM types Asynchronous DRAM FPM RAM EDO RAM Burst EDO RAM Video RAM WRAM Synchronous DRAM SDR SDRAM DDR SDRAM DDR2 SDRAM DDR3 SDRAM DDR4 SDRAM Rambus RAM XDR DRAM XDR2 DRAM VC-RAM SGRAM GDDR2 GDDR3 GDDR4 GDDR5 XDR DRAM. XDR DRAM or extreme data rate dynamic random access memory is a high-performance RAM interface and successor to the Rambus RDRAM it is based on, competing with the rival DDR2 SDRAM and GDDR4 technology. XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance memory applications, and high-end GPUs. It eliminates the unusually high latency problems that plagued early forms of RDRAM. Also, the XDR DRAM have heavy emphasis on per pin bandwidth, which can benefit further cost control on PCB production. This is because fewer lanes are needed for the same amount of bandwidth. Rambus owns the rights to the technology. XDR is used by Sony in the PlayStation 3 console.[1] Contents [hide] 1 Parameters 1.1 Performance 1.2 Features 1.3 Power requirements 1.4 Ease of system design 1.5 Latency 2 See also 3 References 4 External links [edit] Parameters [edit] Performance Initial clock rate at 400 MHz. 600 MHz, 800 MHz with 1066 MHz planned for the future. Octal Data Rate (ODR): Eight bits per clock per lane. Each chip provides 8, 16, or 32 programmable lanes, providing up to 230.4 Gbit/s (28.8 GB/s) [2] [edit] Features Bi-directional differential Rambus Signalling Levels (DRSL) This uses differential open-collector driver, voltage swing 0.2V. It is not the same as LVDS.[1] Programmable on-chip termination Adaptive impedance matching Eight bank memory architecture Up to four bank-interleaved transactions at full bandwidth Point-to-point data interconnect Chip scale package packaging Dynamic request scheduling Early-read-after-write support for maximum efficiency Zero overhead refresh [edit] Power requirements 1.8 V Vdd Programmable ultra-low-voltage DRSL 200 mV swing Low-power PLL/DLL design Power-down self-refresh support Dynamic data width support with dynamic clock gating Per-pin I/O power-down Sub-page activation support [edit] Ease of system design Per-bit FlexPhase circuits compensate to a 2.5 ps resolution XDR Interconnect uses minimum pin count [edit] Latency 1.25/2.0/2.5/3.33 ns request packets [edit] See also RDRAM XDR2 DRAM List of device bandwidths [edit] References ^ AnandTech: Rambus in Cell Processors and Intel's Dual Core Announcements ^ Elpida Produces World's Fastest 7.2GHz XDR DRAM [edit] External links Rambus XDR Product Page Rambus FlexIO CPU Interface provides XDR Interface Qimonda XDR(TM) DRAM product  This computer hardware-related article is a stub. You can help Wikipedia by expanding it.