[linuxkernelnewbies] High-speed I/O Design Techniques

[Peter Teoh]

http://web.mit.edu/professional/short-programs/courses/high_speed_io_design.html High-Speed I/O Design Techniques [6.22s] Click here for email updates - stay informed about course availability and registration dates. Date: June 8-10, 2009 | Tuition: $2,000 | Continuing Education Units (CEUs): 1.8 Course Summary This course covers the circuit and system design of equalized high-speed I/Os. Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints, and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical, and dynamic system modeling with system architecture, mixed-signal, and digital circuit design. This course will lay the groundwork for this type of system-driven I/O design by covering each of the required layers in link system hierarchy. Basics of channel properties are introduced first followed by modeling, measurements, and communications techniques. The course then focuses on different link equalization techniques, comparing them both from system perspective and from the performance of resulting circuit implementations. Some examples will cover trade-offs between transmit pre-emphasis and decision-feedback equalization, linear analog receiver equalization, as well as joint modulation/equalization and equalization/coding techniques (like PAM4, duobinary and multitone signaling). Implementations of transmitter FIR equalizers, several DFE receiver topologies, and peaking amplifiers will be discussed in detail. Several adaptive techniques for equalizer tuning and link monitoring will also be presented. Content   Fundamentals: Core concepts, understandings and tools (35%)   Latest Developments: Recent advances and future trends (25%)   Industry Applications: Linking theory and real-world (40%) Delivery Methods   Lecture: Delivery of material in a lecture format (50%)   Discussion or Groupwork: Participatory learning (10%)   Labs: Demonstrations, experiments, simulations (40%) Level   Introductory: Appropriate for a general audience (15%)   Specialized: Assumes experience in practice area or field (55%)   Advanced: In-depth explorations at the graduate level (30%) « Back to Top Learning Objectives The participants of this course will be able to: Understand the components of a typical high-speed link channel and relate them to link performance and overall channel response. Construct an open-loop and adaptive equalizer to correct for the channel frequency selectivity. Apply different inter-symbol and noise models and run statistical simulation of link performance. Understand basic concepts in link transmitter and receiver circuit design. Describe trade-offs and design of advanced transmit and receiver equalization circuits. Extract key trade-offs between inter-symbol interference and circuit induced noise for different modulation and equalization techniques. Analyze state-of-the-art methods for link data and clock recovery. Apply adaptive equalization algorithms. Construct a real-time behavioral simulation of critical link blocks (adaptive equalizer, clock and data recovery). Analyze circuit behavior of critical link circuits through circuit simulation. « Back to Top Who Should Attend This course is targeted towards integrated circuit, system, and signal-integrity engineers and students who wish to gain better understanding of all the layers involved in design of high-speed interconnects. It can serve both as an entry point into the area and also as a review of the state-of-the-art practices in high-speed I/O design, both in industry and academia. A basic background in electrical engineering is required. « Back to Top Program Outline This course consists of 2 days of instruction and 1 day of labs in link performance simulation, system and circuit design of most critical blocks. Day 1 Background and Motivation; Link Channel Environment; Equalization and Modulation 1. Introduction 2. Background and Motivation I/O link applications Channel properties Transmitter and receiver overview Circuit limitations 3. Link Channel Environment Description of link channel environment (transmission lines, connectors, packages) Basic transmission line theory Lossy transmission lines (skin-effect, dielectric loss, edge-roughness) Understanding impedance discontinuities and reflections Impact of packages and on-chip terminations Channel component design examples Putting it all together 4. Equalization and Modulation Understanding the inter-symbol interference and cross-talk Linear equalization algorithms Decision feedback equalization algorithms Adaptive equalization Multi-level modulation on bandlimited channels Partial-response signaling Day 2 Link Modeling; Lab 1 1. Link Modeling Overview of current models (worst-case, standard statistical) Accurate statistical modeling of intersymbol-interference and cross-talk Timing noise modeling Bit-error rate modeling 2. Lab 1 Design of linear and decision-feedback equalizers (Matlab simulations) Multi-level signaling Statistical link modeling simulations (Matlab) Adaptive equalization (Matlab/CppSim) Course Participant Dinner at a Local Restaurant Day 3 Link System Implementations (Equalization, Clock Recovery); Lab 2 1. Link System Implementations Link system design (equalizer type trade-offs, adaptive equalization, back-channel) Transmitter implementations (driver design, transmit pre-emphasis) Receiver implementations (pre-amplifier, decision circuits, decision-feedback) Clock and data recovery Link monitoring and adaptation circuits 2. Lab 2 Link behavioral simulations (decision-feedback equalizer and data-recovery) Circuit simulations – filtering and sampling receiver implementations (pre-amplifier, decision circuits, loop-unrolled decision-feedback)