[linuxkernelnewbies] IEEE/ACM International Symposium on Microarchitecture

[Peter Teoh]

http://www.informatik.uni-trier.de/~ley/db/conf/micro/micro2007.html 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA. IEEE Computer Society 2007 BibTeX Technology Issues Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. 3-14 Electronic Edition (link) BibTeX Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks: Process Variation Tolerant 3T1D-Based Cache Architectures. 15-26 Electronic Edition (link) BibTeX Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas: Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. 27-42 Electronic Edition (link) BibTeX Instruction Scheduling Sebastian Winkel: Optimal versus Heuristic Global Code Scheduling. 43-55 Electronic Edition (link) BibTeX Guilherme Ottoni, David I. August: Global Multi-Threaded Instruction Scheduling. 56-68 Electronic Edition (link) BibTeX Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas Jablin, David I. August: Revisiting the Sequential Programming Model for Multi-Core. 69-84 Electronic Edition (link) BibTeX Wear-Out Aware Architectures Jaume Abella, Xavier Vera, Antonio González: Penelope: The NBTI-Aware Processor. 85-96 Electronic Edition (link) BibTeX Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. 97-108 Electronic Edition (link) BibTeX Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke: Self-calibrating Online Wearout Detection. 109-122 Electronic Edition (link) BibTeX Memory Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam: Implementing Signatures for Transactional Memory. 123-133 Electronic Edition (link) BibTeX Mrinmoy Ghosh, Hsien-Hsin S. Lee: Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. 134-145 Electronic Edition (link) BibTeX Onur Mutlu, Thomas Moscibroda: Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. 146-160 Electronic Edition (link) BibTeX Networking and Security Amit Kumar, Ram Huggahalli: Impact of Cache Coherence Protocols on the Processing of Network Traffic. 161-171 Electronic Edition (link) BibTeX John Kim, James D. Balfour, William J. Dally: Flattened Butterfly Topology for On-Chip Networks. 172-182 Electronic Edition (link) BibTeX Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin: Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. 183-196 Electronic Edition (link) BibTeX Reliability Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe: Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. 197-209 Electronic Edition (link) BibTeX Albert Meixner, Michael E. Bauer, Daniel J. Sorin: Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. 210-222 Electronic Edition (link) BibTeX Niti Madan, Rajeev Balasubramonian: Leveraging 3D Technology for Improved Reliability. 223-235 Electronic Edition (link) BibTeX Francisco J. Mesa-Martinez, Jose Renau: Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. 236-248 Electronic Edition (link) BibTeX Simulation/Workload Analysis Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat: FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. 249-261 Electronic Edition (link) BibTeX Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle: Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. 262-271 Electronic Edition (link) BibTeX Chang-Burm Cho, Wangyuan Zhang, Tao Li: Informed Microarchitecture Design Space Exploration Using Workload Dynamics. 274-285 Electronic Edition (link) BibTeX Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan: Time Interpolation: So Many Metrics, So Few Registers. 286-300 Electronic Edition (link) BibTeX Prefetching and Snooping Yuan Chou: Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications. 301-313 Electronic Edition (link) BibTeX Jason Zebchuk, Elham Safi, Andreas Moshovos: A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. 314-327 Electronic Edition (link) BibTeX Karin Strauss, Xiaowei Shen, Josep Torrellas: Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. 327-342 Electronic Edition (link) BibTeX Parallelism and QoS in CMPs Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer: A Framework for Providing Quality of Service in Chip Multi-Processors. 343-355 Electronic Edition (link) BibTeX William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe: A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. 356-369 Electronic Edition (link) BibTeX Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke: Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. 369-380 Electronic Edition (link) BibTeX Parallel Architectures Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler: Composable Lightweight Processors. 381-394 Electronic Edition (link) BibTeX Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman: The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. 394-406 Electronic Edition (link) BibTeX Wilson W. L. Fung, Ivan Sham, George Yuan, Tor M. Aamodt: Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. 407-420 Electronic Edition (link) BibTeX Cache Replacement Policies Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez: Scavenger: A New Last Level Cache Architecture with Global Block Priority. 421-432 Electronic Edition (link) BibTeX Stephen Hines, David B. Whalley, Gary S. Tyson: Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. 433-444 Electronic Edition (link) BibTeX Kaushik Rajan, Govindarajan Ramaswamy: Emulating Optimal Replacement with a Shepherd Cache. 445-454 Electronic Edition (link) BibTeX