Hi Chris, In ARM v4/v5 specification, mul %r0, %r0, %r1 (r0 = r0*r1) is invalid, but mul %r0, %r1, %r0 is valid. With early-clobber constraint, ARM backend wouldn't emit the the mul %r0, %r1, %r0. We need a constraint only for the first source register.
Lauro 2007/1/26, Chris Lattner <[EMAIL PROTECTED]>: > On Jan 26, 2007, at 6:09 AM, Lauro Ramos Venancio wrote: > >> 1. I think rather than adding a constraint that says a source operand > >> must not be assigned the same register as another. It would be better > >> if you add a constraint that says a source operand "can be killed at > >> issue cycle + n". The live range analysis current assumes every > >> source operand read is completed at issue cycle + 0 and write back > >> happens at issue cycle + 2. By changing the read latency to 2 you can > >> force a source operand to conflict with a destination operand. > > > > Currently, kill moment of a temporary is determined by the last use of > > it. With the constraint proposed by you, an intermediary use could > > determine kill moment of a temporary. For example, in an use (with > > read latency 5) of a temporary followed by other use of it (with read > > latency 0), the kill moment would be determined by first use. This > > would complicate liveness algorithm. Does any backend need this > > constraint? > > > > Maybe, it would be better a constraint that changes the kill moment > > from default (can kill at issue cycle + 0) to "can kill after > > instruction execution". What do you think? > > I don't have any useful technical input to provide, but this feature > is quite similar to the GCC "&" early-clobber constraint modifier: > > http://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#Modifiers > > It would be nice if the facility we end up with is at least as > general as it is. > > -Chris > _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
