Hi, I have been trying to change cache line size (to 128) using that option. But I get following error
fatal: port A size 64, port B size 128 Busses don't have the same block size... Not supported. @ cycle 0 [init:build/ALPHA_FS/mem/ bridge.cc, line 99] I don't think just specifying the cacheline_size on command line would work. I have also tried setting the block size of system.tol2bus to 128 but I still get the above error. I am not sure what I am missing. Thanks, Abhishek On Wed, Jun 8, 2011 at 6:34 PM, Nilay Vaish <ni...@cs.wisc.edu> wrote: > On Wed, 8 Jun 2011, prasanth wrote: > > Hi, >> >> I am using MESI_CMP_directory protocol. I would like to change the cache >> block >> size in L1 cache and L2 cache to 1 word to simplify some techniques which >> I am >> experimenting on. >> >> For the Classic Memory System, configs/common/CacheConfig.py file sets the >> block >> sizes of L1 and L2 caches. But I wasn't able to find the places to modify >> for >> Ruby Memory System. >> >> In src/mem/ruby/system/Cache.py, Ruby Cache class sets start_index_bit >> which is >> related to the cache line size. Is this the one to be modified? >> >> regards, >> >> Prasanth >> >> > There is an option for specifying the cacheline size, namely, > cacheline_size. It defaults to 64 bytes. You can set it on the command line. > > -- > Nilay > > _______________________________________________ > gem5-users mailing list > gem5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- -Abhishek Graduate Student Computer Science University of Virginia --------------------------------------------------------------------------------------------------------------------- simplicity is the ultimate sophistication -Leonardo da Vinci
_______________________________________________ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
