> > I'm looking to share the framebuffer between the ARM CPU and DSP and > > therefore would like to ask a few questions about the ARM MMU and in > > particular TLBs. > > Most probably it is related to DSP MMU not ARM MMU but I am not sure. > Until now I thought TLB (translation look-aside buffer) is > dynamic thing > you mostly don't care about just like L2 or L1 CPU cache (Well unless > you read LWN of course :-) see > http://lwn.net/SubscriberLink/255364/65f972b0422f379b/ ).
I had thought the same thing, which is (partly) why I was confused :) > Since the message "TLB full" did not make sense to me at all I did a > google check and got this > http://focus.ti.com/lit/an/swpa038/swpa038.pdf That's an interesting document I'd not seen. Thanks for the link. > So it looks like DSP TLB is set up manually for fast access > and indeed > it may be full. Well it's certainly not completely full - it's possible to map smaller memory chunks (i.e. see my shared memory example code I sent to the list a few weeks ago, which runs on both 770 and N800). > I think TLB on main (ARM) cpu is too precious to be locked in > this way > since it is needed for every access to memory by every > process. Yes, that was my thought too. > I guess > it really may be DSP MMU where it make more sense. Makes more sense yes. I'll have to take another look at the kernel code and check this is what's happening. If so, the wording of the output message in dmesg is a little misleading. There are also 32 TLBs on the DSP. The kernel code makes reference to locking TLBs (and says that the last one can't be locked) so this indicates that it's referring to the DSP's MMU. I'll do some more code reading. > 770 has framebuffer mapped for DSP because there are video codecs > implemented as DSP tasks. This is no longer true with N800 so mapping > for DSP makes little sense. With N800 some (or all? video one > at least) > planes are even mapped to SRAM not normal SDRAM like with 770 > so maybe > it is even not accessible by DSP (not sure about this > limitation at all). Yes, that's why it's not mapped, but there shouldn't necessarily be any reason why it can't be remapped and used (e.g. for colourspace conversion), which is my goal. > know how to solve this. Maybe the set of DSP tasks on N800 > are coded to > use TLB fully since framebuffer acces is not needed. Still > the rest free > TLB entries may be enough if it is possible to use them in > dynamic way > but it will be slower. That's how I understand it. >From the pdf it looks like I should be able to map a section of 1 Megabytes and that should use a single TLB on the DSP (and we know there are ~6 TLBs available). There's a gap in the N800's memory space (in the same location as the 770's FRAMEBUFFER section) which is 0x100000 bytes long (whether these are 8- or 16-bit bytes is anyone's guess). I'll try mapping this section and report what happens. Thanks, Simon _______________________________________________ maemo-developers mailing list maemo-developers@maemo.org https://lists.maemo.org/mailman/listinfo/maemo-developers
