We don't need these for GLSL or ARB, but we need them for SPIR-V
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 6d15c60..4ae403c 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -104,6 +104,11 @@ brw_compiler_create(void *mem_ctx, const struct
brw_device_info *devinfo)
nir_options->lower_ffma = true;
nir_options->lower_sub = true;
nir_options->lower_fdiv = true;
+ nir_options->lower_scmp = true;
+ nir_options->lower_fmod = true;
+ nir_options->lower_bitfield_insert = true;
+ nir_options->lower_uadd_carry = true;
+ nir_options->lower_usub_borrow = true;
/* In the vec4 backend, our dpN instruction replicates its result to all
* the components of a vec4. We would like NIR to give us replicated fdot
--
2.5.0.400.gff86faf
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