For simulating less capable machines.
---
src/gallium/auxiliary/gallivm/lp_bld_init.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index ab55be4..6e08ac4 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -399,6 +399,20 @@ lp_build_init(void)
util_cpu_detect();
+ /* For simulating less capable machines */
+#ifdef DEBUG
+ if (debug_get_bool_option("LP_FORCE_SSE2", FALSE)) {
+ assert(util_cpu_caps.has_sse2);
+ util_cpu_caps.has_sse3 = 0;
+ util_cpu_caps.has_ssse3 = 0;
+ util_cpu_caps.has_sse4_1 = 0;
+ util_cpu_caps.has_sse4_2 = 0;
+ util_cpu_caps.has_avx = 0;
+ util_cpu_caps.has_avx2 = 0;
+ util_cpu_caps.has_f16c = 0;
+ }
+#endif
+
/* AMD Bulldozer AVX's throughput is the same as SSE2; and because using
* 8-wide vector needs more floating ops than 4-wide (due to padding), it is
* actually more efficient to use 4-wide vectors on this processor.
@@ -456,17 +470,6 @@ lp_build_init(void)
gallivm_initialized = TRUE;
-#if 0
- /* For simulating less capable machines */
- util_cpu_caps.has_sse3 = 0;
- util_cpu_caps.has_ssse3 = 0;
- util_cpu_caps.has_sse4_1 = 0;
- util_cpu_caps.has_sse4_2 = 0;
- util_cpu_caps.has_avx = 0;
- util_cpu_caps.has_avx2 = 0;
- util_cpu_caps.has_f16c = 0;
-#endif
-
return TRUE;
}
--
2.5.0
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