On Wednesday, June 1, 2016 2:44:58 PM PDT Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand <ja...@jlekstrand.net>
> Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
> Cc: Ian Romanick <i...@freedesktop.org>
> ---
> src/intel/vulkan/gen7_pipeline.c | 12 ++++++++++--
> src/intel/vulkan/gen8_pipeline.c | 12 ++++++++++--
> src/intel/vulkan/genX_pipeline_util.h | 30 +++++++++++++++++++++++++++++-
> 3 files changed, 49 insertions(+), 5 deletions(-)
>
> diff --git a/src/intel/vulkan/gen7_pipeline.c
> b/src/intel/vulkan/gen7_pipeline.c
> index 243b18b..0d2d086 100644
> --- a/src/intel/vulkan/gen7_pipeline.c
> +++ b/src/intel/vulkan/gen7_pipeline.c
> @@ -155,6 +155,8 @@ genX(graphics_pipeline_create)(
> VkPipeline* pPipeline)
> {
> ANV_FROM_HANDLE(anv_device, device, _device);
> + ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
> + struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
> struct anv_pipeline *pipeline;
> VkResult result;
>
> @@ -178,7 +180,7 @@ genX(graphics_pipeline_create)(
> assert(pCreateInfo->pRasterizationState);
> gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
>
> - emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
> + emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
>
> gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
> pCreateInfo->pMultisampleState);
> @@ -369,10 +371,16 @@ genX(graphics_pipeline_create)(
> wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
> wm.PixelShaderUsesInputCoverageMask =
> wm_prog_data->uses_sample_mask;
>
> + /* TODO: We could probably do something a bit more intellegent here.
> + * However, CTS tests expect that if earliy fragment tests are not
> + * performed, the shader *will* be executed for every fragment. In
> + * order to work around this we would have to check whether or not
> + * the shader has side-effects before we can set the mode to NORMAL.
> + */That's what we do in i965 - we should really do it for anv as well...
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