Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.
Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex on HSW
Signed-off-by: Jason Ekstrand <ja...@jlekstrand.net>
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: Francisco Jerez <curroje...@riseup.net>
---
src/intel/genxml/gen75.xml | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 27112b6..1debc3a 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2951,6 +2951,7 @@
<register name="CHICKEN3" length="1" num="0xe49c">
<field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
+ <field name="L3 Atomic Disable Mask" start="22" end="22" type="uint"/>
</register>
</genxml>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index b6f93e7..6a84383 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -296,6 +296,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer,
anv_pack_struct(&scratch1, GENX(SCRATCH1),
.L3AtomicDisable = !has_dc);
anv_pack_struct(&chicken3, GENX(CHICKEN3),
+ .L3AtomicDisableMask = true,
.L3AtomicDisable = !has_dc);
emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1);
emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3);
--
2.5.0.400.gff86faf
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