On Tue, Jun 20, 2017 at 3:24 PM, Chad Versace <chadvers...@chromium.org>
wrote:
> On Fri 16 Jun 2017, Jason Ekstrand wrote:
> > While we're here, we also make the two support checks static since there
> > are no users outside intel_mipmap_tree.c.
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45
> +++++++++++++--------------
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++---------
> > 3 files changed, 25 insertions(+), 40 deletions(-)
>
> This patch greatly clarifies the code, making it more precise. I'm
> always in favor for replacing fuzzy, english phrases in code with
> terse, precise terms.
>
>
> > @@ -734,8 +732,8 @@ intel_miptree_create(struct brw_context *brw,
> > * clear actually occurs or when compressed single sampled buffer is
> > * written by the GPU for the first time.
> > */
> > - if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
> > - intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
> > + if (intel_tiling_supports_ccs(brw, mt->tiling) &&
> > + intel_miptree_supports_ccs(brw, mt)) {
>
> That was my favorite hunk of the patch. Now it's obvious the the two
> lines are checking essentially the same thing. In fact, we can probably
> drop the tiling check here. The miptree check should be sufficient (and
> if it's not, that's a bug in my opinion).
>
If only... Unfortunately, we need intel_miptree_supports_ccs to *not* know
about tiling because we have to decide whether or not to do CCS so that we
can deside if we need HALIGN16 so that we can layout the miptree so that we
can decide tiling. Yes, it's terrible.
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