Both patches: Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
On 27.06.2017 18:56, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_compute.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 91a6a40..fba02fa 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -713,21 +713,24 @@ static void si_emit_dispatch_packets(struct si_context *sctx, radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0])); radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1])); radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));unsigned dispatch_initiator =S_00B800_COMPUTE_SHADER_EN(1) | - S_00B800_FORCE_START_AT_000(1); + S_00B800_FORCE_START_AT_000(1) | + /* If the KMD allows it (there is a KMD hw register for it), + * allow launching waves out-of-order. (same as Vulkan) */ + S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK);if (info->indirect) {uint64_t base_va = r600_resource(info->indirect)->gpu_address;radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,(struct r600_resource *)info->indirect, RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |PKT3_SHADER_TYPE_S(1));
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