From: Dave Airlie <airl...@redhat.com>
Move all calculations to shader generation.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 22 +++++++++++++---------
src/amd/vulkan/radv_pipeline.c | 8 ++------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 923bfaabb97..b6c84390a1e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -83,7 +83,6 @@ struct radv_shader_context {
LLVMValueRef tcs_offchip_layout;
LLVMValueRef tcs_out_offsets;
- LLVMValueRef tcs_out_layout;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -355,13 +354,22 @@ get_tcs_in_patch_stride(struct radv_shader_context *ctx)
static LLVMValueRef
get_tcs_out_patch_stride(struct radv_shader_context *ctx)
{
- return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
+ uint32_t num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ uint32_t num_tcs_patch_outputs =
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+ uint32_t output_vertex_size = num_tcs_outputs * 16;
+ uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch *
output_vertex_size;
+ uint32_t output_patch_size = pervertex_output_patch_size +
num_tcs_patch_outputs * 16;
+ output_patch_size /= 4;
+ return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
}
static LLVMValueRef
get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
{
- return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
+ uint32_t num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ uint32_t output_vertex_size = num_tcs_outputs * 16;
+ output_vertex_size /= 4;
+ return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
}
static LLVMValueRef
@@ -533,7 +541,7 @@ static void allocate_user_sgprs(struct radv_shader_context
*ctx,
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count +=
count_vs_user_sgprs(ctx);
}
- user_sgpr_info->sgpr_count += 3;
+ user_sgpr_info->sgpr_count += 2;
break;
case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
@@ -804,8 +812,6 @@ static void create_function(struct radv_shader_context *ctx,
&ctx->tcs_offchip_layout);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_out_offsets);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tcs_out_layout);
if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index);
@@ -827,8 +833,6 @@ static void create_function(struct radv_shader_context *ctx,
&ctx->tcs_offchip_layout);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_out_offsets);
- add_arg(&args, ARG_SGPR, ctx->ac.i32,
- &ctx->tcs_out_layout);
if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->abi.view_index);
@@ -1037,7 +1041,7 @@ static void create_function(struct radv_shader_context
*ctx,
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
previous_stage, &user_sgpr_idx);
- set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx,
3);
+ set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx,
2);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx,
1);
break;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 79a9c1f6c87..d51b191788d 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -62,7 +62,6 @@ struct radv_blend_state {
struct radv_tessellation_state {
uint32_t ls_hs_config;
- uint32_t tcs_out_layout;
uint32_t tcs_out_offsets;
uint32_t offchip_layout;
unsigned num_patches;
@@ -1382,8 +1381,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.lds_size = lds_size;
- tess.tcs_out_layout = (output_patch_size / 4) |
- ((output_vertex_size / 4) << 13);
tess.tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16)
|
@@ -2615,12 +2612,11 @@ radv_pipeline_generate_tess_shaders(struct
radeon_winsys_cs *cs,
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL,
AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
uint32_t base_reg =
pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
- assert(loc->num_sgprs == 3);
+ assert(loc->num_sgprs == 2);
assert(!loc->indirect);
- radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 3);
+ radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 2);
radeon_emit(cs, tess->offchip_layout);
radeon_emit(cs, tess->tcs_out_offsets);
- radeon_emit(cs, tess->tcs_out_layout);
}
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL,
AC_UD_TES_OFFCHIP_LAYOUT);
--
2.14.3
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