On Thursday, March 7, 2019 2:23:53 PM PST Axel Davy wrote:
> I do not see any perf impact on radeonsi, but it
> seems iris needs this.
> It seems something sensible to do.
> 
> Signed-off-by: Axel Davy <davyax...@gmail.com>
> Reviewed-by: Timur Kristóf <timur.kris...@gmail.com>
> Tested-by: Andre Heider <a.hei...@gmail.com>
> ---
> It may be argued this kind of stuff should be done in the driver.
> I don't mind either way. The ogl state tracker already does that
> optimization.
>  src/gallium/state_trackers/nine/nine_pipe.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/state_trackers/nine/nine_pipe.c 
> b/src/gallium/state_trackers/nine/nine_pipe.c
> index a84a17f551f..b69ddb67113 100644
> --- a/src/gallium/state_trackers/nine/nine_pipe.c
> +++ b/src/gallium/state_trackers/nine/nine_pipe.c
> @@ -36,8 +36,11 @@ nine_convert_dsa_state(struct 
> pipe_depth_stencil_alpha_state *dsa_state,
>  
>      if (rs[D3DRS_ZENABLE]) {
>          dsa.depth.enabled = 1;
> -        dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE];
>          dsa.depth.func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ZFUNC]);
> +        /* Disable depth write if no change can occur */
> +        dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE] &&
> +            dsa.depth.func != PIPE_FUNC_EQUAL &&
> +            dsa.depth.func != PIPE_FUNC_NEVER;
>      }
>  
>      if (rs[D3DRS_STENCILENABLE]) {
> 

I don't think we actually need the NEVER check, but it seems fine.

Patches 1 and 3 are:
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

I'm not really up to speed to review the others.

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