Also changed a couple of direct shifts into SET_FIELD().
Fixes: arb_copy_image-formats -auto -fbo on ILK. In principle,
minimum level settings are only for TextureView to use. We,
however, also take advantage of that internally when blitting.
Before this patch this wasn't taken into account for ILK in the
surface setup.
v2:
- Removed extra whitespace and switched tabs to spaces (Matt)
- Added assertion on minimum level (Ken).
Reviewed-by: Matt Turner <matts...@gmail.com> (v1)
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> (v1)
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 37 +++++++++++++++--------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 ++++-----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 10 +++---
4 files changed, 36 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 5d853d5..d7a1faf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -985,8 +985,9 @@ struct brw_context
{
void (*update_texture_surface)(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
GLenum target, uint32_t effective_depth,
+ uint32_t min_layer,
+ uint32_t min_lod, uint32_t mip_count,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 84f4aa5..2ffeb7f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -310,13 +310,14 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj, GLenum target,
+ GLenum target,
uint32_t effective_depth /* unused */,
+ uint32_t min_layer /* unused */,
+ uint32_t min_lod, uint32_t mip_count,
uint32_t tex_format, int swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -358,16 +359,16 @@ brw_update_texture_surface(struct brw_context *brw,
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT
|
- (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = SET_FIELD(mip_count, BRW_SURFACE_LOD) |
+ SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
+ SET_FIELD(mt->logical_height0 - 1, BRW_SURFACE_HEIGHT);
- surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
- (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
+ SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+ SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
- surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(tObj->BaseLevel - mt->first_level,
BRW_SURFACE_MIN_LOD));
+ surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
+ SET_FIELD(min_lod, BRW_SURFACE_MIN_LOD);
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
@@ -831,9 +832,19 @@ update_texture_surface(struct gl_context *ctx,
uint32_t effective_depth = (tObj->Immutable && tObj->Target !=
GL_TEXTURE_3D)
? tObj->NumLayers : mt->logical_depth0;
- brw->vtbl.update_texture_surface(brw, mt, tObj, tObj->Target,
- effective_depth, tex_format,
- swizzle, surf_offset, for_gather);
+ const uint32_t mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
+ const uint32_t min_lod = tObj->MinLevel + tObj->BaseLevel - mt->first_level;
+
+ /* Minimum level is only supported for TextureView but internally it is
+ * also taken advantage of by meta blit path. The former is only enabled
+ * from gen7 onwards.
+ */
+ assert(brw->gen >= 7 || tObj->MinLevel == 0 || brw->meta_in_progress);
+
+ brw->vtbl.update_texture_surface(brw, mt, tObj->Target,
+ effective_depth, tObj->MinLayer,
+ min_lod, mip_count, tex_format, swizzle,
+ surf_offset, for_gather);
}
static void
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 0769ab8..1fe7a05 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -266,14 +266,13 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
static void
gen7_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
GLenum target, uint32_t effective_depth,
+ uint32_t min_layer,
+ uint32_t min_lod, uint32_t mip_count,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
-
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 32, surf_offset);
memset(surf, 0, 8 * 4);
@@ -312,14 +311,13 @@ gen7_update_texture_surface(struct brw_context *brw,
surf[3] |= HSW_SURFACE_IS_INTEGER_FORMAT;
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
- SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
+ SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD((effective_depth - 1),
GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
- surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
- SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level,
GEN7_SURFACE_MIN_LOD) |
- /* mip count */
- (intelObj->_MaxLevel - tObj->BaseLevel));
+ surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+ SET_FIELD(min_lod, GEN7_SURFACE_MIN_LOD) |
+ mip_count;
surf[7] = mt->fast_clear_color_value;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index fa8a5e6..739d9bc 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -152,13 +152,13 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
static void
gen8_update_texture_surface(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
GLenum target, uint32_t effective_depth,
+ uint32_t min_layer,
+ uint32_t min_lod, uint32_t mip_count,
uint32_t tex_format, int swizzle,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
struct intel_mipmap_tree *aux_mt = NULL;
uint32_t aux_mode = 0;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
@@ -199,13 +199,11 @@ gen8_update_texture_surface(struct brw_context *brw,
surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
- SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
+ SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD(effective_depth - 1,
GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
- surf[5] = SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level,
- GEN7_SURFACE_MIN_LOD) |
- (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
+ surf[5] = SET_FIELD(min_lod, GEN7_SURFACE_MIN_LOD) | mip_count;
if (aux_mt) {
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
--
1.9.3
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