Hello, Could you update CVS / GIT / BZR, thank you
PS : Don't hesitate to correct the document if you found some mistakes
#if !defined(__msp430_headers_usci_h__) #define __msp430_headers_usci_h__ /* usi.h * * mspgcc project: MSP430 device headers * USCI module header * * (c) 2006 by Steve Underwood <ste...@coppice.org> * Originally based in part on work by Texas Instruments Inc. * * $Id: usci.h,v 1.7 2009/06/04 21:55:18 cliechti Exp $ * * 2008-02-05 - modifications by G.Lemm <msp...@daqtix.com> * - added UC1IE and UC1IFG registers * - added UC*1*IE and UC*1*IFG bit definitions * 2009-05-19 - modifications by S. Balling <prakti...@innoventis.de> * - added switch for USCI0 * - added USCI0_5 * - added USCI1_5 : tbd * - added USCI2_5 : tbd * - added USCI3_5 : tbd * * 2009-09-08 - THLN * - definition updated with flexible base address * - USCI0_5 to USCI3_5 definition updated * based on Texas Instruments document : "MSP430x5xx Family User's Guide - SLAU208 Revised July 2010" * */ /* Switches: __MSP430_HAS_USCI0__ - if device has USCI0 __MSP430_HAS_USCI1__ - if device has USCI1 __MSP430_HAS_USCI0_5__ - if device has USCI0 and is part of family 5 __MSP430_HAS_USCI1_5__ - if device has USCI1 and is part of family 5 __MSP430_HAS_USCI2_5__ - if device has USCI2 and is part of family 5 __MSP430_HAS_USCI3_5__ - if device has USCI3 and is part of family 5 __MSP430_UCA0_BASE__ - define base address of UCA0 module (default is 0x5c0). __MSP430_UCB0_BASE__ - define base address of UCB0 module (default is 0x5e0). __MSP430_UCA1_BASE__ - define base address of UCA1 module (default is 0x600). __MSP430_UCB1_BASE__ - define base address of UCB1 module (default is 0x620). __MSP430_UCA2_BASE__ - define base address of UCA2 module (default is 0x640). __MSP430_UCB2_BASE__ - define base address of UCB1 module (default is 0x660). __MSP430_UCA3_BASE__ - define base address of UCA3 module (default is 0x680). __MSP430_UCB3_BASE__ - define base address of UCB3 module (default is 0x6a0). */ #define USIPE7 (0x80) /* USI Port Enable Px.7 */ #define USIPE6 (0x40) /* USI Port Enable Px.6 */ #define USIPE5 (0x20) /* USI Port Enable Px.5 */ #define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */ #define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */ #define USIGE (0x04) /* USI General Output Enable Latch */ #define USIOE (0x02) /* USI Output Enable */ #define USISWRST (0x01) /* USI Software Reset */ #define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */ #define USII2C (0x40) /* USI I2C Mode */ #define USISTTIE (0x20) /* USI START Condition interrupt enable */ #define USIIE (0x10) /* USI Counter Interrupt enable */ #define USIAL (0x08) /* USI Arbitration Lost */ #define USISTP (0x04) /* USI STOP Condition received */ #define USISTTIFG (0x02) /* USI START Condition interrupt Flag */ #define USIIFG (0x01) /* USI Counter Interrupt Flag */ #define USIDIV2 (0x80) /* USI Clock Divider 2 */ #define USIDIV1 (0x40) /* USI Clock Divider 1 */ #define USIDIV0 (0x20) /* USI Clock Divider 0 */ #define USISSEL2 (0x10) /* USI Clock Source Select 2 */ #define USISSEL1 (0x08) /* USI Clock Source Select 1 */ #define USISSEL0 (0x04) /* USI Clock Source Select 0 */ #define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */ #define USISWCLK (0x01) /* USI Software Clock */ #define USIDIV_0 (0x00) /* USI Clock Divider: 0 */ #define USIDIV_1 (0x20) /* USI Clock Divider: 1 */ #define USIDIV_2 (0x40) /* USI Clock Divider: 2 */ #define USIDIV_3 (0x60) /* USI Clock Divider: 3 */ #define USIDIV_4 (0x80) /* USI Clock Divider: 4 */ #define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */ #define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */ #define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */ #define USISSEL_0 (0x00) /* USI Clock Source: 0 */ #define USISSEL_1 (0x04) /* USI Clock Source: 1 */ #define USISSEL_2 (0x08) /* USI Clock Source: 2 */ #define USISSEL_3 (0x0C) /* USI Clock Source: 3 */ #define USISSEL_4 (0x10) /* USI Clock Source: 4 */ #define USISSEL_5 (0x14) /* USI Clock Source: 5 */ #define USISSEL_6 (0x18) /* USI Clock Source: 6 */ #define USISSEL_7 (0x1C) /* USI Clock Source: 7 */ #define USISCLREL (0x80) /* USI SCL Released */ #define USI16B (0x40) /* USI 16 Bit Shift Register Enable */ #define USIFGDC (0x20) /* USI Interrupt Flag don't clear */ #define USICNT4 (0x10) /* USI Bit Count 4 */ #define USICNT3 (0x08) /* USI Bit Count 3 */ #define USICNT2 (0x04) /* USI Bit Count 2 */ #define USICNT1 (0x02) /* USI Bit Count 1 */ #define USICNT0 (0x01) /* USI Bit Count 0 */ // UART-Mode Bits #define UCPEN (0x80) /* Async. Mode: Parity enable */ #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ // SPI-Mode Bits #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ #define UCMST (0x08) /* Sync. Mode: Master Select */ // I2C-Mode Bits #define UCA10 (0x80) /* 10-bit Address Mode */ #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ #define UCMM (0x20) /* Multi-Master Environment */ //#define res (0x10) /* reserved */ #define UCMODE_0 (0<<1) /* Sync. Mode: USCI Mode: 0 */ #define UCMODE_1 (1<<1) /* Sync. Mode: USCI Mode: 1 */ #define UCMODE_2 (2<<1) /* Sync. Mode: USCI Mode: 2 */ #define UCMODE_3 (3<<1) /* Sync. Mode: USCI Mode: 3 */ // UART-Mode Bits #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ #define UCRXEIE (0x20) /* RX Error interrupt enable */ #define UCBRKIE (0x10) /* Break interrupt enable */ #define UCDORM (0x08) /* Dormant (Sleep) Mode */ #define UCTXADDR (0x04) /* Send next Data as Address */ #define UCTXBRK (0x02) /* Send next Data as Break */ #define UCSWRST (0x01) /* USCI Software Reset */ // SPI-Mode Bits //#define res (0x20) /* reserved */ //#define res (0x10) /* reserved */ //#define res (0x08) /* reserved */ //#define res (0x04) /* reserved */ //#define res (0x02) /* reserved */ // I2C-Mode Bits //#define res (0x20) /* reserved */ #define UCTR (0x10) /* Transmit/Receive Select/Flag */ #define UCTXNACK (0x08) /* Transmit NACK */ #define UCTXSTP (0x04) /* Transmit STOP */ #define UCTXSTT (0x02) /* Transmit START */ #define UCSSEL_0 (0<<6) /* USCI 0 Clock Source: 0 */ #define UCSSEL_1 (1<<6) /* USCI 0 Clock Source: 1 */ #define UCSSEL_2 (2<<6) /* USCI 0 Clock Source: 2 */ #define UCSSEL_3 (3<<6) /* USCI 0 Clock Source: 3 */ #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ #define UCBRF_0 (0x0<<4) /* USCI First Stage Modulation: 0 */ #define UCBRF_1 (0x1<<4) /* USCI First Stage Modulation: 1 */ #define UCBRF_2 (0x2<<4) /* USCI First Stage Modulation: 2 */ #define UCBRF_3 (0x3<<4) /* USCI First Stage Modulation: 3 */ #define UCBRF_4 (0x4<<4) /* USCI First Stage Modulation: 4 */ #define UCBRF_5 (0x5<<4) /* USCI First Stage Modulation: 5 */ #define UCBRF_6 (0x6<<4) /* USCI First Stage Modulation: 6 */ #define UCBRF_7 (0x7<<4) /* USCI First Stage Modulation: 7 */ #define UCBRF_8 (0x8<<4) /* USCI First Stage Modulation: 8 */ #define UCBRF_9 (0x9<<4) /* USCI First Stage Modulation: 9 */ #define UCBRF_10 (0xA<<4) /* USCI First Stage Modulation: A */ #define UCBRF_11 (0xB<<4) /* USCI First Stage Modulation: B */ #define UCBRF_12 (0xC<<4) /* USCI First Stage Modulation: C */ #define UCBRF_13 (0xD<<4) /* USCI First Stage Modulation: D */ #define UCBRF_14 (0xE<<4) /* USCI First Stage Modulation: E */ #define UCBRF_15 (0xF<<4) /* USCI First Stage Modulation: F */ #define UCBRS_0 (0<<1) /* USCI Second Stage Modulation: 0 */ #define UCBRS_1 (1<<1) /* USCI Second Stage Modulation: 1 */ #define UCBRS_2 (2<<1) /* USCI Second Stage Modulation: 2 */ #define UCBRS_3 (3<<1) /* USCI Second Stage Modulation: 3 */ #define UCBRS_4 (4<<1) /* USCI Second Stage Modulation: 4 */ #define UCBRS_5 (5<<1) /* USCI Second Stage Modulation: 5 */ #define UCBRS_6 (6<<1) /* USCI Second Stage Modulation: 6 */ #define UCBRS_7 (7<<1) /* USCI Second Stage Modulation: 7 */ #define UCLISTEN (0x80) /* USCI Listen mode */ #define UCFE (0x40) /* USCI Frame Error Flag */ #define UCOE (0x20) /* USCI Overrun Error Flag */ #define UCPE (0x10) /* USCI Parity Error Flag */ #define UCBRK (0x08) /* USCI Break received */ #define UCRXERR (0x04) /* USCI RX Error Flag */ #define UCADDR (0x02) /* USCI Address received Flag */ #define UCBUSY (0x01) /* USCI Busy Flag */ #define UCIDLE (0x02) /* USCI Idle line detected Flag */ //#define res (0x80) /* reserved */ //#define res (0x40) /* reserved */ //#define res (0x20) /* reserved */ //#define res (0x10) /* reserved */ #define UCNACKIE (0x08) /* NACK Condition interrupt enable */ #define UCSTPIE (0x04) /* STOP Condition interrupt enable */ #define UCSTTIE (0x02) /* START Condition interrupt enable */ #define UCALIE (0x01) /* Arbitration Lost interrupt enable */ #define UCSCLLOW (0x40) /* SCL low */ #define UCGC (0x20) /* General Call address received Flag */ #define UCBBUSY (0x10) /* Bus Busy Flag */ #define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ #define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ #define UCSTTIFG (0x02) /* START Condition interrupt Flag */ #define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ //#define res (0x80) /* reserved */ //#define res (0x40) /* reserved */ #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ #define UCSTOE (0x08) /* Sync-Field Timeout error */ #define UCBTOE (0x04) /* Break Timeout error */ //#define res (0x02) /* reserved */ #define UCABDEN (0x01) /* Auto Baud Rate detect enable */ #define UCGCEN (0x8000) /* I2C General Call enable */ #define UCOA9 (0x0200) /* I2C Own Address 9 */ #define UCOA8 (0x0100) /* I2C Own Address 8 */ #define UCOA7 (0x0080) /* I2C Own Address 7 */ #define UCOA6 (0x0040) /* I2C Own Address 6 */ #define UCOA5 (0x0020) /* I2C Own Address 5 */ #define UCOA4 (0x0010) /* I2C Own Address 4 */ #define UCOA3 (0x0008) /* I2C Own Address 3 */ #define UCOA2 (0x0004) /* I2C Own Address 2 */ #define UCOA1 (0x0002) /* I2C Own Address 1 */ #define UCOA0 (0x0001) /* I2C Own Address 0 */ #define UCSA9 (0x0200) /* I2C Slave Address 9 */ #define UCSA8 (0x0100) /* I2C Slave Address 8 */ #define UCSA7 (0x0080) /* I2C Slave Address 7 */ #define UCSA6 (0x0040) /* I2C Slave Address 6 */ #define UCSA5 (0x0020) /* I2C Slave Address 5 */ #define UCSA4 (0x0010) /* I2C Slave Address 4 */ #define UCSA3 (0x0008) /* I2C Slave Address 3 */ #define UCSA2 (0x0004) /* I2C Slave Address 2 */ #define UCSA1 (0x0002) /* I2C Slave Address 1 */ #define UCSA0 (0x0001) /* I2C Slave Address 0 */ /* Aliases by mspgcc */ #define UCSSEL_UCLKI UCSSEL_0 #define UCSSEL_ACLK UCSSEL_1 #define UCSSEL_SMCLK UCSSEL_2 #if defined(__MSP430_HAS_USCI0__) /* -------- USCI0 */ #define UCA0CTL0_ 0x0060 /* USCI A0 Control Register 0 */ sfrb(UCA0CTL0, UCA0CTL0_); #define UCA0CTL1_ 0x0061 /* USCI A0 Control Register 1 */ sfrb(UCA0CTL1, UCA0CTL1_); #define UCA0BR0_ 0x0062 /* USCI A0 Baud Rate 0 */ sfrb(UCA0BR0, UCA0BR0_); #define UCA0BR1_ 0x0063 /* USCI A0 Baud Rate 1 */ sfrb(UCA0BR1, UCA0BR1_); #define UCA0MCTL_ 0x0064 /* USCI A0 Modulation Control */ sfrb(UCA0MCTL, UCA0MCTL_); #define UCA0STAT_ 0x0065 /* USCI A0 Status Register */ sfrb(UCA0STAT, UCA0STAT_); #define UCA0RXBUF_ 0x0066 /* USCI A0 Receive Buffer */ /*READ_ONLY*/ sfrb(UCA0RXBUF, UCA0RXBUF_); #define UCA0TXBUF_ 0x0067 /* USCI A0 Transmit Buffer */ sfrb(UCA0TXBUF, UCA0TXBUF_); #define UCA0ABCTL_ 0x005D /* USCI A0 Auto baud/LIN Control */ sfrb(UCA0ABCTL, UCA0ABCTL_); #define UCA0IRTCTL_ 0x005E /* USCI A0 IrDA Transmit Control */ sfrb(UCA0IRTCTL, UCA0IRTCTL_); #define UCA0IRRCTL_ 0x005F /* USCI A0 IrDA Receive Control */ sfrb(UCA0IRRCTL, UCA0IRRCTL_); #define UCB0CTL0_ 0x0068 /* USCI B0 Control Register 0 */ sfrb(UCB0CTL0, UCB0CTL0_); #define UCB0CTL1_ 0x0069 /* USCI B0 Control Register 1 */ sfrb(UCB0CTL1, UCB0CTL1_); #define UCB0BR0_ 0x006A /* USCI B0 Baud Rate 0 */ sfrb(UCB0BR0, UCB0BR0_); #define UCB0BR1_ 0x006B /* USCI B0 Baud Rate 1 */ sfrb(UCB0BR1, UCB0BR1_); #define UCB0I2CIE_ 0x006C /* USCI B0 I2C Interrupt Enable Register */ sfrb(UCB0I2CIE, UCB0I2CIE_); #define UCB0STAT_ 0x006D /* USCI B0 Status Register */ sfrb(UCB0STAT, UCB0STAT_); #define UCB0RXBUF_ 0x006E /* USCI B0 Receive Buffer */ /*READ_ONLY*/ sfrb(UCB0RXBUF, UCB0RXBUF_); #define UCB0TXBUF_ 0x006F /* USCI B0 Transmit Buffer */ sfrb(UCB0TXBUF, UCB0TXBUF_); #define UCB0I2COA_ 0x0118 /* USCI B0 I2C Own Address */ sfrw(UCB0I2COA, UCB0I2COA_); #define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */ sfrw(UCB0I2CSA, UCB0I2CSA_); #endif /* __MSP430_HAS_USCI0__ */ #if defined(__MSP430_HAS_USCI1__) /* -------- USCI1 */ #define UCA1CTL0_ 0x00D0 /* USCI A1 Control Register 0 */ sfrb(UCA1CTL0, UCA1CTL0_); #define UCA1CTL1_ 0x00D1 /* USCI A1 Control Register 1 */ sfrb(UCA1CTL1, UCA1CTL1_); #define UCA1BR0_ 0x00D2 /* USCI A1 Baud Rate 0 */ sfrb(UCA1BR0, UCA1BR0_); #define UCA1BR1_ 0x00D3 /* USCI A1 Baud Rate 1 */ sfrb(UCA1BR1, UCA1BR1_); #define UCA1MCTL_ 0x00D4 /* USCI A1 Modulation Control */ sfrb(UCA1MCTL, UCA1MCTL_); #define UCA1STAT_ 0x00D5 /* USCI A1 Status Register */ sfrb(UCA1STAT, UCA1STAT_); #define UCA1RXBUF_ 0x00D6 /* USCI A1 Receive Buffer */ /*READ_ONLY*/ sfrb(UCA1RXBUF, UCA1RXBUF_); #define UCA1TXBUF_ 0x00D7 /* USCI A1 Transmit Buffer */ sfrb(UCA1TXBUF, UCA1TXBUF_); #define UCA1ABCTL_ 0x00CD /* USCI A1 Auto baud/LIN Control */ sfrb(UCA1ABCTL, UCA1ABCTL_); #define UCA1IRTCTL_ 0x00CE /* USCI A1 IrDA Transmit Control */ sfrb(UCA1IRTCTL, UCA1IRTCTL_); #define UCA1IRRCTL_ 0x00CF /* USCI A1 IrDA Receive Control */ sfrb(UCA1IRRCTL, UCA1IRRCTL_); #define UCB1CTL0_ 0x00D8 /* USCI B1 Control Register 0 */ sfrb(UCB1CTL0, UCB1CTL0_); #define UCB1CTL1_ 0x00D9 /* USCI B1 Control Register 1 */ sfrb(UCB1CTL1, UCB1CTL1_); #define UCB1BR0_ 0x00DA /* USCI B1 Baud Rate 0 */ sfrb(UCB1BR0, UCB1BR0_); #define UCB1BR1_ 0x00DB /* USCI B1 Baud Rate 1 */ sfrb(UCB1BR1, UCB1BR1_); #define UCB1I2CIE_ 0x00DC /* USCI B1 I2C Interrupt Enable Register */ sfrb(UCB1I2CIE, UCB1I2CIE_); #define UCB1STAT_ 0x00DD /* USCI B1 Status Register */ sfrb(UCB1STAT, UCB1STAT_); #define UCB1RXBUF_ 0x00DE /* USCI B1 Receive Buffer */ /*READ_ONLY*/ sfrb(UCB1RXBUF, UCB1RXBUF_); #define UCB1TXBUF_ 0x00DF /* USCI B1 Transmit Buffer */ sfrb(UCB1TXBUF, UCB1TXBUF_); #define UCB1I2COA_ 0x017C /* USCI B1 I2C Own Address */ sfrw(UCB1I2COA, UCB1I2COA_); #define UCB1I2CSA_ 0x017E /* USCI B1 I2C Slave Address */ sfrw(UCB1I2CSA, UCB1I2CSA_); #define UC1IE_ 0x0006 /* USCI A1/B1 Interrupt enable register */ sfrb(UC1IE, UC1IE_); #define UC1IFG_ 0x0007 /* USCI A1/B1 Interrupt flag register */ sfrb(UC1IFG, UC1IFG_); #define UCA1RXIE (1<<0) #define UCA1TXIE (1<<1) #define UCB1RXIE (1<<2) #define UCB1TXIE (1<<3) #define UCA1RXIFG (1<<0) #define UCA1TXIFG (1<<1) #define UCB1RXIFG (1<<2) #define UCB1TXIFG (1<<3) #endif /* __MSP430_HAS_USCI1__ */ #if defined(__MSP430_HAS_USCI0_5__) /* USCI A0 base address */ #if !defined(__MSP430_UCA0_BASE__) #define __MSP430_UCA0_BASE__ 0x5c0 #endif #define UCA0CTLW0_ __MSP430_UCA0_BASE__ + 0x0 /* USCI A0 Control Word 0 Register */ sfrw(UCA0CTLW0, UCA0CTLW0_); #define UCA0CTLW0_L_ __MSP430_UCA0_BASE__ + 0x0 /* USCI A0 Control Word 0 Register Lo */ sfrb(UCA0CTLW0_L, UCA0CTLW0_L_); #define UCA0CTLW0_H_ __MSP430_UCA0_BASE__ + 0x1 /* USCI A0 Control Word 0 Register Hi */ sfrb(UCA0CTLW0_H, UCA0CTLW0_H_); #define UCA0CTL1_ __MSP430_UCA0_BASE__ + 0x0 /* USCI A0 Control 1 Register */ sfrb(UCA0CTL1, UCA0CTL1_); #define UCA0CTL0_ __MSP430_UCA0_BASE__ + 0x1 /* USCI A0 Control 0 Register */ sfrb(UCA0CTL0, UCA0CTL0_); #define UCA0BRW_ __MSP430_UCA0_BASE__ + 0x6 /* USCI A0 Baud Rate Control Word Register */ sfrw(UCA0BRW, UCA0BRW_); #define UCA0BRW_L_ __MSP430_UCA0_BASE__ + 0x6 /* USCI A0 Baud Rate Control Word Register Lo */ sfrb(UCA0BRW_L, UCA0BRW_L_); #define UCA0BRW_H_ __MSP430_UCA0_BASE__ + 0x7 /* USCI A0 Baud Rate Control Word Register Hi */ sfrb(UCA0BRW_H, UCA0BRW_H_); #define UCA0BR0_ __MSP430_UCA0_BASE__ + 0x6 /* USCI A0 Baud Rate Control 0 Register */ sfrb(UCA0BR0, UCA0BR0_); #define UCA0BR1_ __MSP430_UCA0_BASE__ + 0x7 /* USCI A0 Baud Rate Control 1 Register */ sfrb(UCA0BR1, UCA0BR1_); #define UCA0MCTL_ __MSP430_UCA0_BASE__ + 0x8 /* USCI A0 Modulation Control Register */ sfrb(UCA0MCTL, UCA0MCTL_); #define UCA0STAT_ __MSP430_UCA0_BASE__ + 0xa /* USCI A0 Status Register */ sfrb(UCA0STAT, UCA0STAT_); #define UCA0RXBUF_ __MSP430_UCA0_BASE__ + 0xc /* USCI A0 Receive Buffer Register */ sfrb(UCA0RXBUF, UCA0RXBUF_); #define UCA0TXBUF_ __MSP430_UCA0_BASE__ + 0xe /* USCI A0 Transmit Buffer Register */ sfrb(UCA0TXBUF, UCA0TXBUF_); #define UCA0ABCTL_ __MSP430_UCA0_BASE__ + 0x10 /* USCI A0 Auto Baud Rate Control Register */ sfrb(UCA0ABCTL, UCA0ABCTL_); #define UCA0IRCTL_ __MSP430_UCA0_BASE__ + 0x12 /* USCI A0 IrDA Control Register */ sfrw(UCA0IRCTL, UCA0IRCTL_); #define UCA0IRCTL_L_ __MSP430_UCA0_BASE__ + 0x12 /* USCI A0 IrDA Control Register Lo */ sfrb(UCA0IRCTL_L, UCA0IRCTL_L_); #define UCA0IRCTL_H_ __MSP430_UCA0_BASE__ + 0x13 /* USCI A0 IrDA Control Register Hi */ sfrb(UCA0IRCTL_H, UCA0IRCTL_H_); #define UCA0IRTCTL_ __MSP430_UCA0_BASE__ + 0x12 /* USCI A0 IrDA Transmit Register */ sfrb(UCA0IRTCTL, UCA0IRTCTL_); #define UCA0IRRCTL_ __MSP430_UCA0_BASE__ + 0x13 /* USCI A0 IrDA Receive Register */ sfrb(UCA0IRRCTL, UCA0IRRCTL_); #define UCA0ICTL_ __MSP430_UCA0_BASE__ + 0x1c /* USCI A0 Interrupt Control Register */ sfrw(UCA0ICTL, UCA0ICTL_); #define UCA0ICTL_L_ __MSP430_UCA0_BASE__ + 0x1c /* USCI A0 Interrupt Control Register Lo */ sfrb(UCA0ICTL_L, UCA0ICTL_L_); #define UCA0ICTL_H_ __MSP430_UCA0_BASE__ + 0x1d /* USCI A0 Interrupt Control Register Hi */ sfrb(UCA0ICTL_H, UCA0ICTL_H_); #define UCA0IE_ __MSP430_UCA0_BASE__ + 0x1c /* USCI A0 Interrupt Enable Register */ sfrb(UCA0IE, UCA0IE_); #define UCA0IFG_ __MSP430_UCA0_BASE__ + 0x1d /* USCI A0 Interrupt Flag Register */ sfrb(UCA0IFG, UCA0IFG_); #define UCA0IV_ __MSP430_UCA0_BASE__ + 0x1e /* USCI A0 Interrupt Vector Register */ sfrw(UCA0IV, UCA0IV_); #define UCA0IV_L_ __MSP430_UCA0_BASE__ + 0x1e /* USCI A0 Interrupt Vector Register Lo */ sfrb(UCA0IV_L, UCA0IV_L_); #define UCA0IV_H_ __MSP430_UCA0_BASE__ + 0x1f /* USCI A0 Interrupt Vector Register Hi */ sfrb(UCA0IV_H, UCA0IV_H_); /* USCI B0 base address */ #if !defined(__MSP430_UCB0_BASE__) #define __MSP430_UCB0_BASE__ 0x5e0 #endif #define UCB0CTLW0_ __MSP430_UCB0_BASE__ + 0x0 /* USCI B0 Control Word 0 Register */ sfrw(UCB0CTLW0, UCB0CTLW0_); #define UCB0CTLW0_L_ __MSP430_UCB0_BASE__ + 0x0 /* USCI B0 Control Word 0 Register Lo */ sfrb(UCB0CTLW0_L, UCB0CTLW0_L_); #define UCB0CTLW0_H_ __MSP430_UCB0_BASE__ + 0x1 /* USCI B0 Control Word 0 Register Hi */ sfrb(UCB0CTLW0_H, UCB0CTLW0_H_); #define UCB0CTL1_ __MSP430_UCB0_BASE__ + 0x0 /* USCI B0 Control 1 Register */ sfrb(UCB0CTL1, UCB0CTL1_); #define UCB0CTL0_ __MSP430_UCB0_BASE__ + 0x1 /* USCI B0 Control 0 Register */ sfrb(UCB0CTL0, UCB0CTL0_); #define UCB0BRW_ __MSP430_UCB0_BASE__ + 0x6 /* USCI B0 Bit Rate Control Word Register */ sfrw(UCB0BRW, UCB0BRW_); #define UCB0BRW_L_ __MSP430_UCB0_BASE__ + 0x6 /* USCI B0 Bit Rate Control Word Register Lo */ sfrb(UCB0BRW_L, UCB0BRW_L_); #define UCB0BRW_H_ __MSP430_UCB0_BASE__ + 0x7 /* USCI B0 Bit Rate Control Word Register Hi */ sfrb(UCB0BRW_H, UCB0BRW_H_); #define UCB0BR0_ __MSP430_UCB0_BASE__ + 0x6 /* USCI B0 Bit Rate Control 0 Register */ sfrb(UCB0BR0, UCB0BR0_); #define UCB0BR1_ __MSP430_UCB0_BASE__ + 0x7 /* USCI B0 Bit Rate Control 1 Register */ sfrb(UCB0BR1, UCB0BR1_); #define UCB0STAT_ __MSP430_UCB0_BASE__ + 0xa /* USCI B0 Status Register */ sfrb(UCB0STAT, UCB0STAT_); #define UCB0RXBUF_ __MSP430_UCB0_BASE__ + 0xc /* USCI B0 Receive Buffer Register */ sfrb(UCB0RXBUF, UCB0RXBUF_); #define UCB0TXBUF_ __MSP430_UCB0_BASE__ + 0xe /* USCI B0 Transmit Buffer Register */ sfrb(UCB0TXBUF, UCB0TXBUF_); #define UCB0I2COA_ __MSP430_UCB0_BASE__ + 0x10 /* USCI B0 I²C Own Address Register */ sfrw(UCB0I2COA, UCB0I2COA_); #define UCB0I2COA_L_ __MSP430_UCB0_BASE__ + 0x10 /* USCI B0 I²C Own Address Register Lo */ sfrb(UCB0I2COA_L, UCB0I2COA_L_); #define UCB0I2COA_H_ __MSP430_UCB0_BASE__ + 0x11 /* USCI B0 I²C Own Address Register Hi */ sfrb(UCB0I2COA_H, UCB0I2COA_H_); #define UCB0I2CSA_ __MSP430_UCB0_BASE__ + 0x12 /* USCI B0 I²C Slave Address Register */ sfrw(UCB0I2CSA, UCB0I2CSA_); #define UCB0I2CSA_L_ __MSP430_UCB0_BASE__ + 0x12 /* USCI B0 I²C Slave Address Register Lo */ sfrb(UCB0I2CSA_L, UCB0I2CSA_L_); #define UCB0I2CSA_H_ __MSP430_UCB0_BASE__ + 0x13 /* USCI B0 I²C Slave Address Register Hi */ sfrb(UCB0I2CSA_H, UCB0I2CSA_H_); #define UCB0ICTL_ __MSP430_UCB0_BASE__ + 0x1c /* USCI B0 Interrupt Control Register */ sfrw(UCB0ICTL, UCB0ICTL_); #define UCB0ICTL_L_ __MSP430_UCB0_BASE__ + 0x1c /* USCI B0 Interrupt Control Register Lo */ sfrb(UCB0ICTL_L, UCB0ICTL_L_); #define UCB0ICTL_H_ __MSP430_UCB0_BASE__ + 0x1d /* USCI B0 Interrupt Control Register Hi */ sfrb(UCB0ICTL_H, UCB0ICTL_H_); #define UCB0IE_ __MSP430_UCB0_BASE__ + 0x1c /* USCI B0 Interrupt Enable Register */ sfrb(UCB0IE, UCB0IE_); #define UCB0IFG_ __MSP430_UCB0_BASE__ + 0x1d /* USCI B0 Interrupt Flag Register */ sfrb(UCB0IFG, UCB0IFG_); #define UCB0IV_ __MSP430_UCB0_BASE__ + 0x1e /* USCI B0 Interrupt Vector Register */ sfrw(UCB0IV, UCB0IV_); #define UCB0IV_L_ __MSP430_UCB0_BASE__ + 0x1e /* USCI B0 Interrupt Vector Register Lo */ sfrb(UCB0IV_L, UCB0IV_L_); #define UCB0IV_H_ __MSP430_UCB0_BASE__ + 0x1f /* USCI B0 Interrupt Vector Register Hi */ sfrb(UCB0IV_H, UCB0IV_H_); #endif /* __MSP430_HAS_USCI0_5__ */ #if defined(__MSP430_HAS_USCI1_5__) /* USCI A1 base address */ #if !defined(__MSP430_UCA1_BASE__) #define __MSP430_UCA1_BASE__ 0x600 #endif #define UCA1CTLW0_ __MSP430_UCA1_BASE__ + 0x0 /* USCI A1 Control Word 0 Register */ sfrw(UCA1CTLW0, UCA1CTLW0_); #define UCA1CTLW0_L_ __MSP430_UCA1_BASE__ + 0x0 /* USCI A1 Control Word 0 Register Lo */ sfrb(UCA1CTLW0_L, UCA1CTLW0_L_); #define UCA1CTLW0_H_ __MSP430_UCA1_BASE__ + 0x1 /* USCI A1 Control Word 0 Register Hi */ sfrb(UCA1CTLW0_H, UCA1CTLW0_H_); #define UCA1CTL1_ __MSP430_UCA1_BASE__ + 0x0 /* USCI A1 Control 1 Register */ sfrb(UCA1CTL1, UCA1CTL1_); #define UCA1CTL0_ __MSP430_UCA1_BASE__ + 0x1 /* USCI A1 Control 0 Register */ sfrb(UCA1CTL0, UCA1CTL0_); #define UCA1BRW_ __MSP430_UCA1_BASE__ + 0x6 /* USCI A1 Baud Rate Control Word Register */ sfrw(UCA1BRW, UCA1BRW_); #define UCA1BRW_L_ __MSP430_UCA1_BASE__ + 0x6 /* USCI A1 Baud Rate Control Word Register Lo */ sfrb(UCA1BRW_L, UCA1BRW_L_); #define UCA1BRW_H_ __MSP430_UCA1_BASE__ + 0x7 /* USCI A1 Baud Rate Control Word Register Hi */ sfrb(UCA1BRW_H, UCA1BRW_H_); #define UCA1BR0_ __MSP430_UCA1_BASE__ + 0x6 /* USCI A1 Baud Rate Control 0 Register */ sfrb(UCA1BR0, UCA1BR0_); #define UCA1BR1_ __MSP430_UCA1_BASE__ + 0x7 /* USCI A1 Baud Rate Control 1 Register */ sfrb(UCA1BR1, UCA1BR1_); #define UCA1MCTL_ __MSP430_UCA1_BASE__ + 0x8 /* USCI A1 Modulation Control Register */ sfrb(UCA1MCTL, UCA1MCTL_); #define UCA1STAT_ __MSP430_UCA1_BASE__ + 0xa /* USCI A1 Status Register */ sfrb(UCA1STAT, UCA1STAT_); #define UCA1RXBUF_ __MSP430_UCA1_BASE__ + 0xc /* USCI A1 Receive Buffer Register */ sfrb(UCA1RXBUF, UCA1RXBUF_); #define UCA1TXBUF_ __MSP430_UCA1_BASE__ + 0xe /* USCI A1 Transmit Buffer Register */ sfrb(UCA1TXBUF, UCA1TXBUF_); #define UCA1ABCTL_ __MSP430_UCA1_BASE__ + 0x10 /* USCI A1 Auto Baud Rate Control Register */ sfrb(UCA1ABCTL, UCA1ABCTL_); #define UCA1IRCTL_ __MSP430_UCA1_BASE__ + 0x12 /* USCI A1 IrDA Control Register */ sfrw(UCA1IRCTL, UCA1IRCTL_); #define UCA1IRCTL_L_ __MSP430_UCA1_BASE__ + 0x12 /* USCI A1 IrDA Control Register Lo */ sfrb(UCA1IRCTL_L, UCA1IRCTL_L_); #define UCA1IRCTL_H_ __MSP430_UCA1_BASE__ + 0x13 /* USCI A1 IrDA Control Register Hi */ sfrb(UCA1IRCTL_H, UCA1IRCTL_H_); #define UCA1IRTCTL_ __MSP430_UCA1_BASE__ + 0x12 /* USCI A1 IrDA Transmit Register */ sfrb(UCA1IRTCTL, UCA1IRTCTL_); #define UCA1IRRCTL_ __MSP430_UCA1_BASE__ + 0x13 /* USCI A1 IrDA Receive Register */ sfrb(UCA1IRRCTL, UCA1IRRCTL_); #define UCA1ICTL_ __MSP430_UCA1_BASE__ + 0x1c /* USCI A1 Interrupt Control Register */ sfrw(UCA1ICTL, UCA1ICTL_); #define UCA1ICTL_L_ __MSP430_UCA1_BASE__ + 0x1c /* USCI A1 Interrupt Control Register Lo */ sfrb(UCA1ICTL_L, UCA1ICTL_L_); #define UCA1ICTL_H_ __MSP430_UCA1_BASE__ + 0x1d /* USCI A1 Interrupt Control Register Hi */ sfrb(UCA1ICTL_H, UCA1ICTL_H_); #define UCA1IE_ __MSP430_UCA1_BASE__ + 0x1c /* USCI A1 Interrupt Enable Register */ sfrb(UCA1IE, UCA1IE_); #define UCA1IFG_ __MSP430_UCA1_BASE__ + 0x1d /* USCI A1 Interrupt Flag Register */ sfrb(UCA1IFG, UCA1IFG_); #define UCA1IV_ __MSP430_UCA1_BASE__ + 0x1e /* USCI A1 Interrupt Vector Register */ sfrw(UCA1IV, UCA1IV_); #define UCA1IV_L_ __MSP430_UCA1_BASE__ + 0x1e /* USCI A1 Interrupt Vector Register Lo */ sfrb(UCA1IV_L, UCA1IV_L_); #define UCA1IV_H_ __MSP430_UCA1_BASE__ + 0x1f /* USCI A1 Interrupt Vector Register Hi */ sfrb(UCA1IV_H, UCA1IV_H_); /* USCI B1 base address */ #if !defined(__MSP430_UCB1_BASE__) #define __MSP430_UCB1_BASE__ 0x620 #endif #define UCB1CTLW0_ __MSP430_UCB1_BASE__ + 0x0 /* USCI B1 Control Word 0 Register */ sfrw(UCB1CTLW0, UCB1CTLW0_); #define UCB1CTLW0_L_ __MSP430_UCB1_BASE__ + 0x0 /* USCI B1 Control Word 0 Register Lo */ sfrb(UCB1CTLW0_L, UCB1CTLW0_L_); #define UCB1CTLW0_H_ __MSP430_UCB1_BASE__ + 0x1 /* USCI B1 Control Word 0 Register Hi */ sfrb(UCB1CTLW0_H, UCB1CTLW0_H_); #define UCB1CTL1_ __MSP430_UCB1_BASE__ + 0x0 /* USCI B1 Control 1 Register */ sfrb(UCB1CTL1, UCB1CTL1_); #define UCB1CTL0_ __MSP430_UCB1_BASE__ + 0x1 /* USCI B1 Control 0 Register */ sfrb(UCB1CTL0, UCB1CTL0_); #define UCB1BRW_ __MSP430_UCB1_BASE__ + 0x6 /* USCI B1 Bit Rate Control Word Register */ sfrw(UCB1BRW, UCB1BRW_); #define UCB1BRW_L_ __MSP430_UCB1_BASE__ + 0x6 /* USCI B1 Bit Rate Control Word Register Lo */ sfrb(UCB1BRW_L, UCB1BRW_L_); #define UCB1BRW_H_ __MSP430_UCB1_BASE__ + 0x7 /* USCI B1 Bit Rate Control Word Register Hi */ sfrb(UCB1BRW_H, UCB1BRW_H_); #define UCB1BR0_ __MSP430_UCB1_BASE__ + 0x6 /* USCI B1 Bit Rate Control 0 Register */ sfrb(UCB1BR0, UCB1BR0_); #define UCB1BR1_ __MSP430_UCB1_BASE__ + 0x7 /* USCI B1 Bit Rate Control 1 Register */ sfrb(UCB1BR1, UCB1BR1_); #define UCB1STAT_ __MSP430_UCB1_BASE__ + 0xa /* USCI B1 Status Register */ sfrb(UCB1STAT, UCB1STAT_); #define UCB1RXBUF_ __MSP430_UCB1_BASE__ + 0xc /* USCI B1 Receive Buffer Register */ sfrb(UCB1RXBUF, UCB1RXBUF_); #define UCB1TXBUF_ __MSP430_UCB1_BASE__ + 0xe /* USCI B1 Transmit Buffer Register */ sfrb(UCB1TXBUF, UCB1TXBUF_); #define UCB1I2COA_ __MSP430_UCB1_BASE__ + 0x10 /* USCI B1 I²C Own Address Register */ sfrw(UCB1I2COA, UCB1I2COA_); #define UCB1I2COA_L_ __MSP430_UCB1_BASE__ + 0x10 /* USCI B1 I²C Own Address Register Lo */ sfrb(UCB1I2COA_L, UCB1I2COA_L_); #define UCB1I2COA_H_ __MSP430_UCB1_BASE__ + 0x11 /* USCI B1 I²C Own Address Register Hi */ sfrb(UCB1I2COA_H, UCB1I2COA_H_); #define UCB1I2CSA_ __MSP430_UCB1_BASE__ + 0x12 /* USCI B1 I²C Slave Address Register */ sfrw(UCB1I2CSA, UCB1I2CSA_); #define UCB1I2CSA_L_ __MSP430_UCB1_BASE__ + 0x12 /* USCI B1 I²C Slave Address Register Lo */ sfrb(UCB1I2CSA_L, UCB1I2CSA_L_); #define UCB1I2CSA_H_ __MSP430_UCB1_BASE__ + 0x13 /* USCI B1 I²C Slave Address Register Hi */ sfrb(UCB1I2CSA_H, UCB1I2CSA_H_); #define UCB1ICTL_ __MSP430_UCB1_BASE__ + 0x1c /* USCI B1 Interrupt Control Register */ sfrw(UCB1ICTL, UCB1ICTL_); #define UCB1ICTL_L_ __MSP430_UCB1_BASE__ + 0x1c /* USCI B1 Interrupt Control Register Lo */ sfrb(UCB1ICTL_L, UCB1ICTL_L_); #define UCB1ICTL_H_ __MSP430_UCB1_BASE__ + 0x1d /* USCI B1 Interrupt Control Register Hi */ sfrb(UCB1ICTL_H, UCB1ICTL_H_); #define UCB1IE_ __MSP430_UCB1_BASE__ + 0x1c /* USCI B1 Interrupt Enable Register */ sfrb(UCB1IE, UCB1IE_); #define UCB1IFG_ __MSP430_UCB1_BASE__ + 0x1d /* USCI B1 Interrupt Flag Register */ sfrb(UCB1IFG, UCB1IFG_); #define UCB1IV_ __MSP430_UCB1_BASE__ + 0x1e /* USCI B1 Interrupt Vector Register */ sfrw(UCB1IV, UCB1IV_); #define UCB1IV_L_ __MSP430_UCB1_BASE__ + 0x1e /* USCI B1 Interrupt Vector Register Lo */ sfrb(UCB1IV_L, UCB1IV_L_); #define UCB1IV_H_ __MSP430_UCB1_BASE__ + 0x1f /* USCI B1 Interrupt Vector Register Hi */ sfrb(UCB1IV_H, UCB1IV_H_); #endif /* __MSP430_HAS_USCI1_5__ */ #if defined(__MSP430_HAS_USCI2_5__) /* USCI A2 base address */ #if !defined(__MSP430_UCA2_BASE__) #define __MSP430_UCA2_BASE__ 0x640 #endif #define UCA2CTLW0_ __MSP430_UCA2_BASE__ + 0x0 /* USCI A2 Control Word 0 Register */ sfrw(UCA2CTLW0, UCA2CTLW0_); #define UCA2CTLW0_L_ __MSP430_UCA2_BASE__ + 0x0 /* USCI A2 Control Word 0 Register Lo */ sfrb(UCA2CTLW0_L, UCA2CTLW0_L_); #define UCA2CTLW0_H_ __MSP430_UCA2_BASE__ + 0x1 /* USCI A2 Control Word 0 Register Hi */ sfrb(UCA2CTLW0_H, UCA2CTLW0_H_); #define UCA2CTL1_ __MSP430_UCA2_BASE__ + 0x0 /* USCI A2 Control 1 Register */ sfrb(UCA2CTL1, UCA2CTL1_); #define UCA2CTL0_ __MSP430_UCA2_BASE__ + 0x1 /* USCI A2 Control 0 Register */ sfrb(UCA2CTL0, UCA2CTL0_); #define UCA2BRW_ __MSP430_UCA2_BASE__ + 0x6 /* USCI A2 Baud Rate Control Word Register */ sfrw(UCA2BRW, UCA2BRW_); #define UCA2BRW_L_ __MSP430_UCA2_BASE__ + 0x6 /* USCI A2 Baud Rate Control Word Register Lo */ sfrb(UCA2BRW_L, UCA2BRW_L_); #define UCA2BRW_H_ __MSP430_UCA2_BASE__ + 0x7 /* USCI A2 Baud Rate Control Word Register Hi */ sfrb(UCA2BRW_H, UCA2BRW_H_); #define UCA2BR0_ __MSP430_UCA2_BASE__ + 0x6 /* USCI A2 Baud Rate Control 0 Register */ sfrb(UCA2BR0, UCA2BR0_); #define UCA2BR1_ __MSP430_UCA2_BASE__ + 0x7 /* USCI A2 Baud Rate Control 1 Register */ sfrb(UCA2BR1, UCA2BR1_); #define UCA2MCTL_ __MSP430_UCA2_BASE__ + 0x8 /* USCI A2 Modulation Control Register */ sfrb(UCA2MCTL, UCA2MCTL_); #define UCA2STAT_ __MSP430_UCA2_BASE__ + 0xa /* USCI A2 Status Register */ sfrb(UCA2STAT, UCA2STAT_); #define UCA2RXBUF_ __MSP430_UCA2_BASE__ + 0xc /* USCI A2 Receive Buffer Register */ sfrb(UCA2RXBUF, UCA2RXBUF_); #define UCA2TXBUF_ __MSP430_UCA2_BASE__ + 0xe /* USCI A2 Transmit Buffer Register */ sfrb(UCA2TXBUF, UCA2TXBUF_); #define UCA2ABCTL_ __MSP430_UCA2_BASE__ + 0x10 /* USCI A2 Auto Baud Rate Control Register */ sfrb(UCA2ABCTL, UCA2ABCTL_); #define UCA2IRCTL_ __MSP430_UCA2_BASE__ + 0x12 /* USCI A2 IrDA Control Register */ sfrw(UCA2IRCTL, UCA2IRCTL_); #define UCA2IRCTL_L_ __MSP430_UCA2_BASE__ + 0x12 /* USCI A2 IrDA Control Register Lo */ sfrb(UCA2IRCTL_L, UCA2IRCTL_L_); #define UCA2IRCTL_H_ __MSP430_UCA2_BASE__ + 0x13 /* USCI A2 IrDA Control Register Hi */ sfrb(UCA2IRCTL_H, UCA2IRCTL_H_); #define UCA2IRTCTL_ __MSP430_UCA2_BASE__ + 0x12 /* USCI A2 IrDA Transmit Register */ sfrb(UCA2IRTCTL, UCA2IRTCTL_); #define UCA2IRRCTL_ __MSP430_UCA2_BASE__ + 0x13 /* USCI A2 IrDA Receive Register */ sfrb(UCA2IRRCTL, UCA2IRRCTL_); #define UCA2ICTL_ __MSP430_UCA2_BASE__ + 0x1c /* USCI A2 Interrupt Control Register */ sfrw(UCA2ICTL, UCA2ICTL_); #define UCA2ICTL_L_ __MSP430_UCA2_BASE__ + 0x1c /* USCI A2 Interrupt Control Register Lo */ sfrb(UCA2ICTL_L, UCA2ICTL_L_); #define UCA2ICTL_H_ __MSP430_UCA2_BASE__ + 0x1d /* USCI A2 Interrupt Control Register Hi */ sfrb(UCA2ICTL_H, UCA2ICTL_H_); #define UCA2IE_ __MSP430_UCA2_BASE__ + 0x1c /* USCI A2 Interrupt Enable Register */ sfrb(UCA2IE, UCA2IE_); #define UCA2IFG_ __MSP430_UCA2_BASE__ + 0x1d /* USCI A2 Interrupt Flag Register */ sfrb(UCA2IFG, UCA2IFG_); #define UCA2IV_ __MSP430_UCA2_BASE__ + 0x1e /* USCI A2 Interrupt Vector Register */ sfrw(UCA2IV, UCA2IV_); #define UCA2IV_L_ __MSP430_UCA2_BASE__ + 0x1e /* USCI A2 Interrupt Vector Register Lo */ sfrb(UCA2IV_L, UCA2IV_L_); #define UCA2IV_H_ __MSP430_UCA2_BASE__ + 0x1f /* USCI A2 Interrupt Vector Register Hi */ sfrb(UCA2IV_H, UCA2IV_H_); /* USCI B2 base address */ #if !defined(__MSP430_UCB2_BASE__) #define __MSP430_UCB2_BASE__ 0x660 #endif #define UCB2CTLW0_ __MSP430_UCB2_BASE__ + 0x0 /* USCI B2 Control Word 0 Register */ sfrw(UCB2CTLW0, UCB2CTLW0_); #define UCB2CTLW0_L_ __MSP430_UCB2_BASE__ + 0x0 /* USCI B2 Control Word 0 Register Lo */ sfrb(UCB2CTLW0_L, UCB2CTLW0_L_); #define UCB2CTLW0_H_ __MSP430_UCB2_BASE__ + 0x1 /* USCI B2 Control Word 0 Register Hi */ sfrb(UCB2CTLW0_H, UCB2CTLW0_H_); #define UCB2CTL1_ __MSP430_UCB2_BASE__ + 0x0 /* USCI B2 Control 1 Register */ sfrb(UCB2CTL1, UCB2CTL1_); #define UCB2CTL0_ __MSP430_UCB2_BASE__ + 0x1 /* USCI B2 Control 0 Register */ sfrb(UCB2CTL0, UCB2CTL0_); #define UCB2BRW_ __MSP430_UCB2_BASE__ + 0x6 /* USCI B2 Bit Rate Control Word Register */ sfrw(UCB2BRW, UCB2BRW_); #define UCB2BRW_L_ __MSP430_UCB2_BASE__ + 0x6 /* USCI B2 Bit Rate Control Word Register Lo */ sfrb(UCB2BRW_L, UCB2BRW_L_); #define UCB2BRW_H_ __MSP430_UCB2_BASE__ + 0x7 /* USCI B2 Bit Rate Control Word Register Hi */ sfrb(UCB2BRW_H, UCB2BRW_H_); #define UCB2BR0_ __MSP430_UCB2_BASE__ + 0x6 /* USCI B2 Bit Rate Control 0 Register */ sfrb(UCB2BR0, UCB2BR0_); #define UCB2BR1_ __MSP430_UCB2_BASE__ + 0x7 /* USCI B2 Bit Rate Control 1 Register */ sfrb(UCB2BR1, UCB2BR1_); #define UCB2STAT_ __MSP430_UCB2_BASE__ + 0xa /* USCI B2 Status Register */ sfrb(UCB2STAT, UCB2STAT_); #define UCB2RXBUF_ __MSP430_UCB2_BASE__ + 0xc /* USCI B2 Receive Buffer Register */ sfrb(UCB2RXBUF, UCB2RXBUF_); #define UCB2TXBUF_ __MSP430_UCB2_BASE__ + 0xe /* USCI B2 Transmit Buffer Register */ sfrb(UCB2TXBUF, UCB2TXBUF_); #define UCB2I2COA_ __MSP430_UCB2_BASE__ + 0x10 /* USCI B2 I²C Own Address Register */ sfrw(UCB2I2COA, UCB2I2COA_); #define UCB2I2COA_L_ __MSP430_UCB2_BASE__ + 0x10 /* USCI B2 I²C Own Address Register Lo */ sfrb(UCB2I2COA_L, UCB2I2COA_L_); #define UCB2I2COA_H_ __MSP430_UCB2_BASE__ + 0x11 /* USCI B2 I²C Own Address Register Hi */ sfrb(UCB2I2COA_H, UCB2I2COA_H_); #define UCB2I2CSA_ __MSP430_UCB2_BASE__ + 0x12 /* USCI B2 I²C Slave Address Register */ sfrw(UCB2I2CSA, UCB2I2CSA_); #define UCB2I2CSA_L_ __MSP430_UCB2_BASE__ + 0x12 /* USCI B2 I²C Slave Address Register Lo */ sfrb(UCB2I2CSA_L, UCB2I2CSA_L_); #define UCB2I2CSA_H_ __MSP430_UCB2_BASE__ + 0x13 /* USCI B2 I²C Slave Address Register Hi */ sfrb(UCB2I2CSA_H, UCB2I2CSA_H_); #define UCB2ICTL_ __MSP430_UCB2_BASE__ + 0x1c /* USCI B2 Interrupt Control Register */ sfrw(UCB2ICTL, UCB2ICTL_); #define UCB2ICTL_L_ __MSP430_UCB2_BASE__ + 0x1c /* USCI B2 Interrupt Control Register Lo */ sfrb(UCB2ICTL_L, UCB2ICTL_L_); #define UCB2ICTL_H_ __MSP430_UCB2_BASE__ + 0x1d /* USCI B2 Interrupt Control Register Hi */ sfrb(UCB2ICTL_H, UCB2ICTL_H_); #define UCB2IE_ __MSP430_UCB2_BASE__ + 0x1c /* USCI B2 Interrupt Enable Register */ sfrb(UCB2IE, UCB2IE_); #define UCB2IFG_ __MSP430_UCB2_BASE__ + 0x1d /* USCI B2 Interrupt Flag Register */ sfrb(UCB2IFG, UCB2IFG_); #define UCB2IV_ __MSP430_UCB2_BASE__ + 0x1e /* USCI B2 Interrupt Vector Register */ sfrw(UCB2IV, UCB2IV_); #define UCB2IV_L_ __MSP430_UCB2_BASE__ + 0x1e /* USCI B2 Interrupt Vector Register Lo */ sfrb(UCB2IV_L, UCB2IV_L_); #define UCB2IV_H_ __MSP430_UCB2_BASE__ + 0x1f /* USCI B2 Interrupt Vector Register Hi */ sfrb(UCB2IV_H, UCB2IV_H_); #endif /* __MSP430_HAS_USCI2_5__ */ #if defined(__MSP430_HAS_USCI3_5__) /* USCI A3 base address */ #if !defined(__MSP430_UCA3_BASE__) #define __MSP430_UCA3_BASE__ 0x680 #endif #define UCA3CTLW0_ __MSP430_UCA3_BASE__ + 0x0 /* USCI A3 Control Word 0 Register */ sfrw(UCA3CTLW0, UCA3CTLW0_); #define UCA3CTLW0_L_ __MSP430_UCA3_BASE__ + 0x0 /* USCI A3 Control Word 0 Register Lo */ sfrb(UCA3CTLW0_L, UCA3CTLW0_L_); #define UCA3CTLW0_H_ __MSP430_UCA3_BASE__ + 0x1 /* USCI A3 Control Word 0 Register Hi */ sfrb(UCA3CTLW0_H, UCA3CTLW0_H_); #define UCA3CTL1_ __MSP430_UCA3_BASE__ + 0x0 /* USCI A3 Control 1 Register */ sfrb(UCA3CTL1, UCA3CTL1_); #define UCA3CTL0_ __MSP430_UCA3_BASE__ + 0x1 /* USCI A3 Control 0 Register */ sfrb(UCA3CTL0, UCA3CTL0_); #define UCA3BRW_ __MSP430_UCA3_BASE__ + 0x6 /* USCI A3 Baud Rate Control Word Register */ sfrw(UCA3BRW, UCA3BRW_); #define UCA3BRW_L_ __MSP430_UCA3_BASE__ + 0x6 /* USCI A3 Baud Rate Control Word Register Lo */ sfrb(UCA3BRW_L, UCA3BRW_L_); #define UCA3BRW_H_ __MSP430_UCA3_BASE__ + 0x7 /* USCI A3 Baud Rate Control Word Register Hi */ sfrb(UCA3BRW_H, UCA3BRW_H_); #define UCA3BR0_ __MSP430_UCA3_BASE__ + 0x6 /* USCI A3 Baud Rate Control 0 Register */ sfrb(UCA3BR0, UCA3BR0_); #define UCA3BR1_ __MSP430_UCA3_BASE__ + 0x7 /* USCI A3 Baud Rate Control 1 Register */ sfrb(UCA3BR1, UCA3BR1_); #define UCA3MCTL_ __MSP430_UCA3_BASE__ + 0x8 /* USCI A3 Modulation Control Register */ sfrb(UCA3MCTL, UCA3MCTL_); #define UCA3STAT_ __MSP430_UCA3_BASE__ + 0xa /* USCI A3 Status Register */ sfrb(UCA3STAT, UCA3STAT_); #define UCA3RXBUF_ __MSP430_UCA3_BASE__ + 0xc /* USCI A3 Receive Buffer Register */ sfrb(UCA3RXBUF, UCA3RXBUF_); #define UCA3TXBUF_ __MSP430_UCA3_BASE__ + 0xe /* USCI A3 Transmit Buffer Register */ sfrb(UCA3TXBUF, UCA3TXBUF_); #define UCA3ABCTL_ __MSP430_UCA3_BASE__ + 0x10 /* USCI A3 Auto Baud Rate Control Register */ sfrb(UCA3ABCTL, UCA3ABCTL_); #define UCA3IRCTL_ __MSP430_UCA3_BASE__ + 0x12 /* USCI A3 IrDA Control Register */ sfrw(UCA3IRCTL, UCA3IRCTL_); #define UCA3IRCTL_L_ __MSP430_UCA3_BASE__ + 0x12 /* USCI A3 IrDA Control Register Lo */ sfrb(UCA3IRCTL_L, UCA3IRCTL_L_); #define UCA3IRCTL_H_ __MSP430_UCA3_BASE__ + 0x13 /* USCI A3 IrDA Control Register Hi */ sfrb(UCA3IRCTL_H, UCA3IRCTL_H_); #define UCA3IRTCTL_ __MSP430_UCA3_BASE__ + 0x12 /* USCI A3 IrDA Transmit Register */ sfrb(UCA3IRTCTL, UCA3IRTCTL_); #define UCA3IRRCTL_ __MSP430_UCA3_BASE__ + 0x13 /* USCI A3 IrDA Receive Register */ sfrb(UCA3IRRCTL, UCA3IRRCTL_); #define UCA3ICTL_ __MSP430_UCA3_BASE__ + 0x1c /* USCI A3 Interrupt Control Register */ sfrw(UCA3ICTL, UCA3ICTL_); #define UCA3ICTL_L_ __MSP430_UCA3_BASE__ + 0x1c /* USCI A3 Interrupt Control Register Lo */ sfrb(UCA3ICTL_L, UCA3ICTL_L_); #define UCA3ICTL_H_ __MSP430_UCA3_BASE__ + 0x1d /* USCI A3 Interrupt Control Register Hi */ sfrb(UCA3ICTL_H, UCA3ICTL_H_); #define UCA3IE_ __MSP430_UCA3_BASE__ + 0x1c /* USCI A3 Interrupt Enable Register */ sfrb(UCA3IE, UCA3IE_); #define UCA3IFG_ __MSP430_UCA3_BASE__ + 0x1d /* USCI A3 Interrupt Flag Register */ sfrb(UCA3IFG, UCA3IFG_); #define UCA3IV_ __MSP430_UCA3_BASE__ + 0x1e /* USCI A3 Interrupt Vector Register */ sfrw(UCA3IV, UCA3IV_); #define UCA3IV_L_ __MSP430_UCA3_BASE__ + 0x1e /* USCI A3 Interrupt Vector Register Lo */ sfrb(UCA3IV_L, UCA3IV_L_); #define UCA3IV_H_ __MSP430_UCA3_BASE__ + 0x1f /* USCI A3 Interrupt Vector Register Hi */ sfrb(UCA3IV_H, UCA3IV_H_); /* USCI B3 base address */ #if !defined(__MSP430_UCB3_BASE__) #define __MSP430_UCB3_BASE__ 0x6a0 #endif #define UCB3CTLW0_ __MSP430_UCB3_BASE__ + 0x0 /* USCI B3 Control Word 0 Register */ sfrw(UCB3CTLW0, UCB3CTLW0_); #define UCB3CTLW0_L_ __MSP430_UCB3_BASE__ + 0x0 /* USCI B3 Control Word 0 Register Lo */ sfrb(UCB3CTLW0_L, UCB3CTLW0_L_); #define UCB3CTLW0_H_ __MSP430_UCB3_BASE__ + 0x1 /* USCI B3 Control Word 0 Register Hi */ sfrb(UCB3CTLW0_H, UCB3CTLW0_H_); #define UCB3CTL1_ __MSP430_UCB3_BASE__ + 0x0 /* USCI B3 Control 1 Register */ sfrb(UCB3CTL1, UCB3CTL1_); #define UCB3CTL0_ __MSP430_UCB3_BASE__ + 0x1 /* USCI B3 Control 0 Register */ sfrb(UCB3CTL0, UCB3CTL0_); #define UCB3BRW_ __MSP430_UCB3_BASE__ + 0x6 /* USCI B3 Bit Rate Control Word Register */ sfrw(UCB3BRW, UCB3BRW_); #define UCB3BRW_L_ __MSP430_UCB3_BASE__ + 0x6 /* USCI B3 Bit Rate Control Word Register Lo */ sfrb(UCB3BRW_L, UCB3BRW_L_); #define UCB3BRW_H_ __MSP430_UCB3_BASE__ + 0x7 /* USCI B3 Bit Rate Control Word Register Hi */ sfrb(UCB3BRW_H, UCB3BRW_H_); #define UCB3BR0_ __MSP430_UCB3_BASE__ + 0x6 /* USCI B3 Bit Rate Control 0 Register */ sfrb(UCB3BR0, UCB3BR0_); #define UCB3BR1_ __MSP430_UCB3_BASE__ + 0x7 /* USCI B3 Bit Rate Control 1 Register */ sfrb(UCB3BR1, UCB3BR1_); #define UCB3STAT_ __MSP430_UCB3_BASE__ + 0xa /* USCI B3 Status Register */ sfrb(UCB3STAT, UCB3STAT_); #define UCB3RXBUF_ __MSP430_UCB3_BASE__ + 0xc /* USCI B3 Receive Buffer Register */ sfrb(UCB3RXBUF, UCB3RXBUF_); #define UCB3TXBUF_ __MSP430_UCB3_BASE__ + 0xe /* USCI B3 Transmit Buffer Register */ sfrb(UCB3TXBUF, UCB3TXBUF_); #define UCB3I2COA_ __MSP430_UCB3_BASE__ + 0x10 /* USCI B3 I²C Own Address Register */ sfrw(UCB3I2COA, UCB3I2COA_); #define UCB3I2COA_L_ __MSP430_UCB3_BASE__ + 0x10 /* USCI B3 I²C Own Address Register Lo */ sfrb(UCB3I2COA_L, UCB3I2COA_L_); #define UCB3I2COA_H_ __MSP430_UCB3_BASE__ + 0x11 /* USCI B3 I²C Own Address Register Hi */ sfrb(UCB3I2COA_H, UCB3I2COA_H_); #define UCB3I2CSA_ __MSP430_UCB3_BASE__ + 0x12 /* USCI B3 I²C Slave Address Register */ sfrw(UCB3I2CSA, UCB3I2CSA_); #define UCB3I2CSA_L_ __MSP430_UCB3_BASE__ + 0x12 /* USCI B3 I²C Slave Address Register Lo */ sfrb(UCB3I2CSA_L, UCB3I2CSA_L_); #define UCB3I2CSA_H_ __MSP430_UCB3_BASE__ + 0x13 /* USCI B3 I²C Slave Address Register Hi */ sfrb(UCB3I2CSA_H, UCB3I2CSA_H_); #define UCB3ICTL_ __MSP430_UCB3_BASE__ + 0x1c /* USCI B3 Interrupt Control Register */ sfrw(UCB3ICTL, UCB3ICTL_); #define UCB3ICTL_L_ __MSP430_UCB3_BASE__ + 0x1c /* USCI B3 Interrupt Control Register Lo */ sfrb(UCB3ICTL_L, UCB3ICTL_L_); #define UCB3ICTL_H_ __MSP430_UCB3_BASE__ + 0x1d /* USCI B3 Interrupt Control Register Hi */ sfrb(UCB3ICTL_H, UCB3ICTL_H_); #define UCB3IE_ __MSP430_UCB3_BASE__ + 0x1c /* USCI B3 Interrupt Enable Register */ sfrb(UCB3IE, UCB3IE_); #define UCB3IFG_ __MSP430_UCB3_BASE__ + 0x1d /* USCI B3 Interrupt Flag Register */ sfrb(UCB3IFG, UCB3IFG_); #define UCB3IV_ __MSP430_UCB3_BASE__ + 0x1e /* USCI B3 Interrupt Vector Register */ sfrw(UCB3IV, UCB3IV_); #define UCB3IV_L_ __MSP430_UCB3_BASE__ + 0x1e /* USCI B3 Interrupt Vector Register Lo */ sfrb(UCB3IV_L, UCB3IV_L_); #define UCB3IV_H_ __MSP430_UCB3_BASE__ + 0x1f /* USCI B3 Interrupt Vector Register Hi */ sfrb(UCB3IV_H, UCB3IV_H_); #endif /* __MSP430_HAS_USCI3_5__ */ #endif