On Wed, Dec 3, 2014 at 3:54 PM, Olivier Girard <olgir...@gmail.com> wrote:

> Hi all,
>
> I am currently updating the verification environment of the openMSP430 to
> support the new Redhat/TI GCC toolchain.
>
> The first thing I noticed is that the *crt0* code by default assumes that
> the watchdog WDTCTL register is mapped at 0x015c...
> Does someone knows if there is a magic switch to change the default
> behavior and map the register to 0x0120 ? (I hope to avoid a re-compile of
> the crt0.S stuff)
>
> Here is the snippet:
> "...
> Disassembly of section .text:
>
> 0000c010 <__start>:
>     c010: 31 40 00 04 mov #1024, r1 ;#0x0400
>
> 0000c014 <.Loc.39.1>:
>     c014: b2 40 80 5a mov #23168, &*0x015c* ;#0x5a80
>     c018: 5c 01
> ..."
>

Interesting.

The existing solution is wrong in a couple ways: first the address of
WDTCTL should not be hard-coded (there are three possible locations across
the current set of MCUs, with 0x15c being wrong for non-5xx MCUS including
the new FR2xx/FR4xx ones), and second the reset value can't be hard-coded
because different clock rates are used on different MCUs, and the right bit
pattern for one will leave another misconfigured once the CRT code
completes.

mspgcc worked around the first issue by defining symbols for all the
registers, so they didn't have to be resolved until non-relocatable link
time.  Oddly, Code Composer Studio's linker files do this, but the ones
TI's providing for GCC don't.  (Absence of symbols also complicates
hardware multiply because if symbols were used instead of address values
some of the MPY32 variation points could be eliminated.)

The second issue can be resolved by creating a reset value based on reading
the power-up value.  The code sequence necessary is:

        mov.b   &__WDTCTL, r5
        bis     #0x5a08, r5
        mov     r5, &__wdt_clear_value

unless that doesn't work for the new FR2xx/4xx WDT peripheral.

(Not that this helps you, but somebody should probably file a bug report
against newlib, which is where those files live.)

Peter
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