Thanks for the correction, I hope you guys weren't too disappointed by the music demo video, indeed the corrected links are the ones I intended to give.
Hi Scott! The complicated subject of a Silicon Compiler in the sense of C to a working co-routine in FPGA is what interests me, and I'd not do much with FPGAs unless I had to if it weren't for that possibility. It's quite possible to outcompute, not just out-logic (so to speak) a modern full blown desktop processor like the I7 with such a humble, few watts chip with FPGA. And then there's clever use of logic on top of that, and if you'd want to take a look at for instance a cloud node like the well known AWS f1 compute there's also the possibility to have huge FPGA connected memory and say a hundred times more power for use with a C compiler. My point is that the path actually works in practice, and with a $99,- board (the Parallella) and free vivado (or vitis) tools. The power achievable with that is possible to use for normal C functions, it's quite advanced. Just like with C, a system programmer may get way more mileage out of knowing how to write an efficient DSP procedure for a certain architecture. And even more with FPGA logic: it's quite interesting to see what parallel/pipelining constructions can be made to work with the correct factoring. Theo V. _______________________________________________ dupswapdrop: music-dsp mailing list music-dsp@music.columbia.edu https://lists.columbia.edu/mailman/listinfo/music-dsp
