On Tue, Jun 21, 2016 at 12:37:39PM +0800, Wei Hu (Xavier) wrote: > > > On 2016/6/20 21:04, Leon Romanovsky wrote: > >On Mon, Jun 20, 2016 at 05:48:15PM +0800, Wei Hu (Xavier) wrote: > >> > >>On 2016/6/20 17:27, Leon Romanovsky wrote: > >>>On Mon, Jun 20, 2016 at 03:49:24PM +0800, Wei Hu (Xavier) wrote: > >>>>On 2016/6/20 14:06, Leon Romanovsky wrote: > >>>>>On Mon, Jun 20, 2016 at 12:37:40PM +0800, Wei Hu (Xavier) wrote: > >>>>>>On 2016/6/17 17:58, Leon Romanovsky wrote: > >>>>>>>On Thu, Jun 16, 2016 at 10:35:16PM +0800, Lijun Ou wrote: > >>>>>>>>This patch mainly added icm support for RoCE. It initializes icm > >>>>>>>>which managers the relative memory blocks for RoCE. The data > >>>>>>>>structures of RoCE will be located in it. For example, CQ table, > >>>>>>>>QP table and MTPT table so on. > >>>>>>>> > >>>>>>>>Signed-off-by: Wei Hu <xavier.hu...@huawei.com> > >>>>>>>>Signed-off-by: Nenglong Zhao <zhaonengl...@hisilicon.com> > >>>>>>>>Signed-off-by: Lijun Ou <ouli...@huawei.com> > >>>>>>>>--- > >>>>>>><...> > >>>>>>> > >>>>>>>>+ > >>>>>Another question which you didn't answer [1]. > >>>>> > >>>>>"I wonder if you have the same needs for ICM as it is in mlx4 device. > >>>>>Do you have firmware?" > >>>>> > >>>>>[1] http://marc.info/?l=linux-rdma&m=146545553104913&w=2 > >>>>Hi, Leon > >>>> Now we haven't firmware. > >>>> But hardware still need memory for QPC\CQC\MTPT\mtt etc. > >>>ICM stands for InfiniHost (Interconnect) Context Memory is a specific > >>>memory place to share between host <-> FW and host <-> HW if HW is > >>>aware of specific structures. > >>> > >>>I assume that in your case, it is enough to allocate memory region and > >>>supply it to HW. Am I right? > >>For Our hardware, > >>1. ICM has a memory management method, It's very good for QPC\CQC\MTPT\mtt > >>etc. we need it. > >You need special HW to leverage its. AFAIK it is Mellanox specific. > For our hardware, we use ICM to memory management, the memory shared with > host and HW. > QPC\CQC\MTPT\mtt has specific memory requirement. > QPC\CQC\MTPT need continuous memory. we use ICM to management the block of > memory. It's very good!
I wasn't convinced why do you need to copy whole ICM logic which is specific to Mellanox. Your requirements can be implemented by standard CMA and/or DMA. > >>2. The meomry for QPC\CQC\MTPT\mtt only used for RoCE hardware and driver, > >>we don't want use MR. > >I didn't mean Infiniband MR, but memory region returned from standard > >allocation functions (kmalloc, ...). > > > >>3. Now we haven't firmware, maybe we need it next version. > >You are always invited to add support once it will be needed, no need to > >add it in advance. > > > >Thanks > >
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