Hi,
> try the attached test patch, if this solves your problem then we are
> heading in the right direction.
Thank you. Yes, it solves the problem - as in I can't reproduce it anymore.
I can still see the SWCLK/SWD wiggle on the logic analyzer before the reset
kicks in. From looking at the code and adding some log messages it seems to be
the SWD mode selection. I tried to move the reset before the
stlink_usb_init_mode but that didn't work as expected: reset is activated and
disabled shortly afterwards again. I think the stlink firmware does this
automatically when changing modes.
The reference manual from STM doesn't say anything about which parts of
debugging need the clocks in the core. But because I can't reproduce it
anymore I guess selecting SWD doesn't need the core clocked.
The solution in your patch is in the stlink code. But when my assumption about
the cause is correct, the problem will hit all STM32 users - regardless which
jtag adapter they use. Is there some more generic way to get this behavior?
About automatically setting the bits in DBGMCU_CR:
I added this to my board config:
source [find mem_helper.tcl]
$_TARGETNAME configure -event reset-init {
# allow debugging during sleep/stop/standby modes:
# set DBG_SLEEP, DBG_STOP and DBG_STANDBY bits in DBGMCU_CR
mmw 0xe0042004 0x7 0x0
}
When I now call openocd with reset init, the bits are set automatically. But
this call (and a lot of other stuff like stm32_stlink_load_core_reg_u32) is
done with reset released again. The program on my controller takes some time
to initialize before it begins to sleep. I guess this is the reason why it
works. Is there some way to keep the reset line active until all this
initialization is completely done? This would make sure that it always works
and not just for me.
Kind regards,
Gerd
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