Hi!

I just stumbled upon an old openocd script for initializing an
arm926ejs. (Guruplug).
I am getting the following error (i presume the syntax has changed):
"arm926ejs cp15 0 0 1 0 0x00052078: command requires more arguments"

Can you please help me out on how to fix this error?
The config file was written for openocd 0.2.0, but my interface is not
yet supported on it (ktlink)

Regards,
  Ákos Vandra

akos@FM12BQ:~/Downloads/guruplug-installer/openocd/interface$ cat
iqprogrammer.cfg
#
# Kristech KT-Link
#
# http://www.kristech.eu
#

interface ft2232
#ft2232_device_desc "KT-LINK"
ft2232_layout ktlink
ft2232_vid_pid 0x0403 0x6010
jtag_khz 1000akos@FM12BQ:~/Downloads/guruplug-installer/openocd/interface$


akos@FM12BQ:~/Downloads/guruplug-installer/openocd/target$ cat feroceon.cfg
######################################
# Target:    Marvell Feroceon CPU core
######################################

if { [info exists CHIPNAME] } { 
   set  _CHIPNAME $CHIPNAME
} else {        
   set  _CHIPNAME feroceon
}

if { [info exists ENDIAN] } {   
   set  _ENDIAN $ENDIAN
} else {        
   set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x20a023d3
}

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position
$_TARGETNAME

reset_config trst_and_srst
jtag_nsrst_delay 200
jtag_ntrst_delay 200

akos@FM12BQ:~/Downloads/guruplug-installer/openocd/board$ cat guruplug.cfg*
# Marvell SheevaPlug

#source [find interface/guruplug.cfg]
source [find interface/iqprogrammer.cfg]
source [find target/feroceon.cfg]

$_TARGETNAME configure \
        -work-area-phys 0x10000000 \
        -work-area-size 65536 \
        -work-area-backup 0

arm7_9 dcc_downloads enable

# this assumes the hardware default peripherals location before u-Boot moves it
nand device 0 orion feroceon.cpu 0xd8000000

proc guruplug_init { } {

        jtag_khz 1000

        # We need to assert DBGRQ while holding nSRST down.
        # However DBGACK will be set only when nSRST is released.
        jtag_reset 0 1
        feroceon.cpu arp_examine
        halt 0
        jtag_reset 0 0
        wait_halt

        arm926ejs cp15 0 0 1 0 0x00052078

        mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
        mww 0xD0001404 0x39543000 #  Dunit Control Low Register
        mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register
        mww 0xD000140C 0x00000833 #  DDR SDRAM Timing (High) Register
        mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register
        mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register
        mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register
        mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register
        mww 0xD0001420 0x00000042 #  DDR SDRAM Extended Mode Register
        mww 0xD0001424 0x0000F17F #  Dunit Control High Register
        mww 0xD0001428 0x00085520 #  Dunit Control High Register
        mww 0xD000147c 0x00008552 #  Dunit Control High Register
        mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register
        mww 0xD0001508 0x10000000 #  CS1n Base Register
        mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register
        mww 0xD0001514 0x00000000 #  CS2n Size Register
        mww 0xD000151C 0x00000000 #  CS3n Size Register
        mww 0xD0001494 0x003C0000 #  DDR2 SDRAM ODT Control (Low) Register
        mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister
        mww 0xD000149C 0x0000F80F #  DDR2 Dunit ODT Control Register
        mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register
        mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "
        mww 0xD0020204 0x00000000 #              "

        mww 0xD0010000 0x01111111 #  MPP  0 to 7
        mww 0xD0010004 0x11113322 #  MPP  8 to 15
        mww 0xD0010008 0x00001111 #  MPP 16 to 23

        mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister
        mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register
        mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register

}

proc guruplug_reflash_uboot { } {

        # reflash the u-Boot binary and reboot into it
        guruplug_init
        nand probe 0
        nand erase 0 0 2
        nand write 0 openocd/uboot.bin 0 oob_softecc
        resume

}

proc guruplug_reflash_uboot_env { } {
        # reflash the u-boot environment variables area
        guruplug_init
        nand probe 0
        nand erase 0 2 4
        nand write 0 openocd/uboot-env.bin 0x00040000 oob_softecc
        resume
}

proc guruplug_load_uboot { } {

        # load u-Boot into RAM and execute it
        guruplug_init
        load_image uboot.elf
        verify_image uboot.elf
        resume 0x00600000

}

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