Hello, does anybody know how breakpoints for Cortex M core are internally implemented ?
I have following problem: I have FLASH @ 0x7000_0000 and SRAM @ 0x7400_0000. If I understand correctly ARM documentation, ICode bus interface is only from 0x0000_0000 to 0x1FFF_FFFF. This is the space where I can set HW breakpoints. I can make steps and set SW breakpoints in SRAM without problems. But not in FLASH. I am getting HardFault exception. However, I heard that with Lauterbach debugger, I can make steps in FLASH. So it must be because of different usage of ARM debug module? It seems to me that step in OpenOCD is done through breakpoint, isn't it ? Is there any other posiibility ? Vaclav ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
