Gene Smith wrote: > Gene Smith wrote: > >> I am unable to set h/w breakpoints or step in my new cortex-m3 >> (stm3210e-eval board) now using jlink. It was working OK for a while >> yesterday but now it refuses to do anything. This is with the informal >> patches we were doing a few weeks ago for jlink which seemed to work >> great when debugging an arm7tdmi with same jlink. Have not tried the >> latest trunk version yet. >> >> I have tried resetting everything but no luck in stepping to main. It >> will allow me to set a bp on main but then when I continue or step it >> produces the info message about the flash patch comparator unit. Not >> sure what this means except it thinks all the hw breakpoints are used up >> which I don't think they are since I only set one. >> >> Thanks, >> -gene >> > > Updated svn to current r2003 and fixed the problems above. However, > don't know why I can't reliably go over jtag_khz 470 like I could when > debugging with the same jlink on the str712 demo board (arm7tdmi). With > the arm7 I could set the jtag speed to zero (adaptive) and it worked > great. With cortex-m3 it seems a bit more limited and error prone (but > OK if kept at or below 470). > > Here's what I see when I go over 470 or set it to zero: > > RCLK - adaptive > > Error: AHBAP Cached values: dp_select 0x0, ap_csw 0xa2000012, ap_tar > 0xffffffff > Error: SWJ-DP OVERRUN - check clock or reduce jtag speed > Error: Read MEM_AP_CSW 0x23000052, MEM_AP_TAR 0xe000edf0 > Error: AHBAP Cached values: dp_select 0x0, ap_csw 0xa2000012, ap_tar > 0xffffffff > Error: SWJ-DP OVERRUN - check clock or reduce jtag speed > Error: Read MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40011c00 > Warn : Block read error address 0x40011c00, count 0xe4 > Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar > 0xe000edf0 > Error: SWJ-DP OVERRUN - check clock or reduce jtag speed > Error: Read MEM_AP_CSW 0x23000042, MEM_AP_TAR 0x40011c00 > > Actually I can do most debugging activities at default 500Khz. But if I > try to dump a large memory block (e.g., with insight, mdb etc.) I see > the above errors. In the example above I was looking at memory location > 0x40011c00 and insight was bring in a full screen of values. > > The new shorter state transition tables actually decrases the time for completing memory bus access betwen succesive dr scans using the same jtag_khz. So the OVERRUN becomes more likely.
I will publish a patch that helps against OVERRUNS soon. Best regards Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
