Hi Magnus,
On Mon, Aug 31, 2009 at 05:36:11PM +0200, Magnus Lundin wrote:
>> dap_ap_select(swjdp, 1);
>> before the two lines
>> dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
>> dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
>> in ahbap_debugport_init()
>>
>>
> What happens when you do "dap info 0" from the telnet interface ?
=======
Open On-Chip Debugger
> dap info 0
ap identification register 0x14770001
Type is mem-ap AHB
ap debugbase 0xffffffff
No ROM table present
> dap info 1
ap identification register 0x04770002
Type is mem-ap APB
ap debugbase 0x80000000
ROM table in legacy format
CID3 0xb1, CID2 0x5, CID1 0x10 CID0, 0xd
MEMTYPE system memory not present. Dedicated debug bus
ROMTABLE[0x0] = 0x1003
Component base address 0x80001000, pid4 0x4, start address
0x80001000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0xb, PID1 0xb9, PID0, 0x7
ROMTABLE[0x4] = 0x2003
Component base address 0x80002000, pid4 0x4, start address
0x80002000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0xb, PID1 0xb9, PID0, 0x6
ROMTABLE[0x8] = 0x4003
Component base address 0x80004000, pid4 0x4, start address
0x80004000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0xb, PID1 0xb9, PID0, 0x8
ROMTABLE[0xc] = 0x5003
Component base address 0x80005000, pid4 0x4, start address
0x80005000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0x5b, PID1 0xbc, PID0, 0x8
ROMTABLE[0x10] = 0x6003
Component base address 0x80006000, pid4 0x4, start address
0x80006000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0x5b, PID1 0xb9, PID0, 0x21
ROMTABLE[0x14] = 0x7003
Component base address 0x80007000, pid4 0x4, start address
0x80007000
Component cid1 0x90, class is CoreSight component
CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
PID3 0x0, PID2 0x5b, PID1 0xb9, PID0, 0x22
ROMTABLE[0x18] = 0x8003
Component base address 0x80008000, pid4 0x0, start address
0x80008000
Component cid1 0x0, class is Reserved
CID3 0x0, CID2 0x0, CID1 0x0, CID0, 0x0
PID3 0x0, PID2 0x0, PID1 0x0, PID0, 0x0
ROMTABLE[0x1c] = 0x0
End of ROM table
> dap info 3
ap identification register 0x00000000
No AP found at this apsel 0x3
No ROM table present
=======
>> However, as soon as the code enters cortex_a8_poll() and calls
>>
>> retval = mem_ap_read_atomic_u32(swjdp,
>> OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
>>
>> the implicit swjdp_transaction_endcheck(). Specifically,
>> SSTICKYORUN is set during the first DP_CTRL_STAT read.
>
> So you can read some of the registers, can you read CPUDBG_DSCR ? and
> its value is?
no, it cannot be read. neither from u-boot, nor from the AHB DAP
> Your problems are probably related to the DBGEN signal, this is an input
> to the Cortex_A8 core and controls debug access. There is some
> documentation of this in the Cortex_A8 TRM, but no way to controling it
> from the debug registers defined by ARM.
I see. It's somewhat strange if ARM has all those detailed and fairly
extensive specifications (and the romtable to discover the debugging
capabilities), but then no standard way how DBGEN can be set? That's weird.
After searching the Cortex-A8 TRM, I found Chapter 12.5.10 authentication
status register (0xFB8). Bit 0 of this register is supposed to correspond to
the DBGEN level. Reading this register through 'mdw 0x80005fb8' tells me it is
set to 0xff, which would mean that DBGEN is set.
Also, the SoC has its own SJGTAG_STATUS register that prinets the DBGEN, NIDEN,
SPIDEN, SPNIDEN signals at 0x80008004, and all of those are set to '1'
So what now? Any more ideas?
--
- Harald Welte <lafo...@gnumonks.org> http://laforge.gnumonks.org/
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