Hello community, here is the log from the commit of package xf86-video-intel for openSUSE:Factory checked in at 2012-10-26 17:36:42 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/xf86-video-intel (Old) and /work/SRC/openSUSE:Factory/.xf86-video-intel.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "xf86-video-intel", Maintainer is "" Changes: -------- --- /work/SRC/openSUSE:Factory/xf86-video-intel/xf86-video-intel.changes 2012-10-16 07:23:47.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.xf86-video-intel.new/xf86-video-intel.changes 2012-10-26 17:36:44.000000000 +0200 @@ -1,0 +2,23 @@ +Sat Oct 20 21:10:05 UTC 2012 - [email protected] + +- Update to 2.20.12 + More bug reports, more bug fixes! Perhaps the headline feature is + that with secure batches, coming to a 3.8 kernel near you, we may + finally have the ability to perform updates to the scanout synchronized + to the refresh rate on later SandyBridge and IvyBridge chipsets. It comes + at quite a power cost as we need to keep the GPU out of its power saving + modes, but it should allow legacy vsync to function at last. But this + should allow us to address a longstanding issue with tearing on + SandyBridge+. +- Bugs fixed since 2.20.10: + + Fix component-alpha rendering on IvyBridge, for example subpixel + antialiased glyphs. + https://bugs.freedesktop.org/show_bug.cgi?id=56037 + + Flush before some "pipelined" state changes on gen4. The evidence is + that the same flushes as required on gen5+ are also required for gen4. + https://bugs.freedesktop.org/show_bug.cgi?id=55627 + + Prevent a potential crash when forcing a stall on a busy CPU bo + https://bugs.freedesktop.org/show_bug.cgi?id=56180 +- [Release 2.20.11 contained a typo causing UXA to fail immediately.] + +------------------------------------------------------------------- Old: ---- xf86-video-intel-2.20.10.tar.bz2 New: ---- xf86-video-intel-2.20.12.tar.bz2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ xf86-video-intel.spec ++++++ --- /var/tmp/diff_new_pack.c1JSNS/_old 2012-10-26 17:36:45.000000000 +0200 +++ /var/tmp/diff_new_pack.c1JSNS/_new 2012-10-26 17:36:45.000000000 +0200 @@ -19,7 +19,7 @@ %define glamor 1 Name: xf86-video-intel -Version: 2.20.10 +Version: 2.20.12 Release: 0 Summary: Intel video driver for the Xorg X server License: MIT ++++++ xf86-video-intel-2.20.10.tar.bz2 -> xf86-video-intel-2.20.12.tar.bz2 ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/NEWS new/xf86-video-intel-2.20.12/NEWS --- old/xf86-video-intel-2.20.10/NEWS 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/NEWS 2012-10-20 17:23:26.000000000 +0200 @@ -1,3 +1,27 @@ +Release 2.20.12 (2012-10-20) +============================ +More bug reports, more bug fixes! Perhaps the headline feature is +that with a secure batches, coming to a 3.8 kernel near you, we may +finally have the ability to perform updates to the scanout synchronized +to the refresh rate on later SandyBridge and IvyBridge chipsets. It comes +at quite a power cost as we need to keep the GPU out of its power saving +modes, but it should allow legacy vsync to function at last. But this +should allow us to address a longstanding issue with tearing on +SandyBridge+. + + * Fix component-alpha rendering on IvyBridge, for example subpixel + antialiased glyphs. + https://bugs.freedesktop.org/show_bug.cgi?id=56037 + + * Flush before some "pipelined" state changes on gen4. The evidence is + that the same flushes as required on gen5+ are also required for gen4. + https://bugs.freedesktop.org/show_bug.cgi?id=55627 + + * Prevent a potential crash when forcing a stall on a busy CPU bo + https://bugs.freedesktop.org/show_bug.cgi?id=56180 + +[Release 2.20.11 contained a typo causing UXA to fail immediately.] + Release 2.20.10 (2012-10-14) ============================ The last couple of weeks have been fairly retrospective, a dive into diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/configure.ac new/xf86-video-intel-2.20.12/configure.ac --- old/xf86-video-intel-2.20.10/configure.ac 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/configure.ac 2012-10-20 17:23:26.000000000 +0200 @@ -23,7 +23,7 @@ # Initialize Autoconf AC_PREREQ([2.60]) AC_INIT([xf86-video-intel], - [2.20.10], + [2.20.12], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], [xf86-video-intel]) AC_CONFIG_SRCDIR([Makefile.am]) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/intel_display.c new/xf86-video-intel-2.20.12/src/intel_display.c --- old/xf86-video-intel-2.20.10/src/intel_display.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/intel_display.c 2012-10-20 17:23:26.000000000 +0200 @@ -493,6 +493,8 @@ ErrorF("failed to add fb\n"); return FALSE; } + + drm_intel_bo_disable_reuse(intel->front_buffer); } saved_mode = crtc->mode; @@ -597,6 +599,8 @@ return NULL; } + drm_intel_bo_disable_reuse(intel_crtc->rotate_bo); + intel_crtc->rotate_pitch = rotate_pitch; return intel_crtc->rotate_bo; } @@ -723,6 +727,8 @@ ErrorF("have front buffer\n"); } + drm_intel_bo_disable_reuse(bo); + intel_crtc->scanout_pixmap = ppix; return drmModeAddFB(intel->drmSubFD, ppix->drawable.width, ppix->drawable.height, ppix->drawable.depth, @@ -1494,6 +1500,7 @@ if (ret) goto fail; + drm_intel_bo_disable_reuse(intel->front_buffer); intel->front_pitch = pitch; intel->front_tiling = tiling; @@ -1555,6 +1562,7 @@ new_front->handle, &new_fb_id)) goto error_out; + drm_intel_bo_disable_reuse(new_front); intel_glamor_flush(intel); intel_batch_submit(scrn); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/gen4_render.c new/xf86-video-intel-2.20.12/src/sna/gen4_render.c --- old/xf86-video-intel-2.20.10/src/sna/gen4_render.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/gen4_render.c 2012-10-20 17:23:26.000000000 +0200 @@ -190,7 +190,7 @@ #define SAMPLER_OFFSET(sf, se, mf, me, k) \ ((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * KERNEL_COUNT + (k)) * 64) -static void +static bool gen4_emit_pipelined_pointers(struct sna *sna, const struct sna_composite_op *op, int blend, int kernel); @@ -243,6 +243,7 @@ gen4_emit_pipelined_pointers(sna, op, PictOpAdd, gen4_choose_composite_kernel(PictOpAdd, true, true, op->is_affine)); + OUT_BATCH(MI_FLUSH); OUT_BATCH(GEN4_3DPRIMITIVE | GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | @@ -1222,11 +1223,11 @@ } } -static void +static bool gen4_emit_binding_table(struct sna *sna, uint16_t offset) { if (sna->render_state.gen4.surface_table == offset) - return; + return false; sna->render_state.gen4.surface_table = offset; @@ -1238,9 +1239,11 @@ OUT_BATCH(0); /* sf */ /* Only the PS uses the binding table */ OUT_BATCH(offset*4); + + return true; } -static void +static bool gen4_emit_pipelined_pointers(struct sna *sna, const struct sna_composite_op *op, int blend, int kernel) @@ -1263,7 +1266,7 @@ key = sp | bp << 16; if (key == sna->render_state.gen4.last_pipelined_pointers) - return; + return true; OUT_BATCH(GEN4_3DSTATE_PIPELINED_POINTERS | 5); OUT_BATCH(sna->render_state.gen4.vs); @@ -1275,6 +1278,7 @@ sna->render_state.gen4.last_pipelined_pointers = key; gen4_emit_urb(sna); + return false; } static void @@ -1376,18 +1380,21 @@ const struct sna_composite_op *op, uint16_t wm_binding_table) { + bool flush = false; + if (FLUSH_EVERY_VERTEX) OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); gen4_emit_drawing_rectangle(sna, op); - gen4_emit_binding_table(sna, wm_binding_table); - gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel); + flush |= gen4_emit_binding_table(sna, wm_binding_table); + flush |= gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel); gen4_emit_vertex_elements(sna, op); - if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) { - DBG(("%s: flushing dirty (%d, %d)\n", __FUNCTION__, + if (flush || kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) { + DBG(("%s: flushing dirty (%d, %d), forced? %d\n", __FUNCTION__, kgem_bo_is_dirty(op->src.bo), - kgem_bo_is_dirty(op->mask.bo))); + kgem_bo_is_dirty(op->mask.bo), + flush)); OUT_BATCH(MI_FLUSH); kgem_clear_dirty(&sna->kgem); kgem_bo_mark_dirty(op->dst.bo); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/gen7_render.c new/xf86-video-intel-2.20.12/src/sna/gen7_render.c --- old/xf86-video-intel-2.20.10/src/sna/gen7_render.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/gen7_render.c 2012-10-20 17:23:26.000000000 +0200 @@ -1077,7 +1077,9 @@ gen7_emit_pipe_invalidate(sna); - gen7_emit_cc(sna, gen7_get_blend(PictOpAdd, true, op->dst.format)); + gen7_emit_cc(sna, + GEN7_BLEND(gen7_get_blend(PictOpAdd, true, + op->dst.format))); gen7_emit_wm(sna, gen7_choose_composite_kernel(PictOpAdd, true, true, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/kgem.c new/xf86-video-intel-2.20.12/src/sna/kgem.c --- old/xf86-video-intel-2.20.10/src/sna/kgem.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/kgem.c 2012-10-20 17:23:26.000000000 +0200 @@ -69,6 +69,7 @@ #define DBG_NO_UPLOAD_ACTIVE 0 #define DBG_NO_MAP_UPLOAD 0 #define DBG_NO_RELAXED_FENCING 0 +#define DBG_NO_SECURE_BATCHES 0 #define DBG_DUMP 0 #define SHOW_BATCH 0 @@ -93,7 +94,8 @@ #define IS_USER_MAP(ptr) ((uintptr_t)(ptr) & 2) #define __MAP_TYPE(ptr) ((uintptr_t)(ptr) & 3) -#define LOCAL_I915_PARAM_HAS_SEMAPHORES 20 +#define LOCAL_I915_PARAM_HAS_SEMAPHORES 20 +#define LOCAL_I915_PARAM_HAS_SECURE_BATCHES 23 #define LOCAL_I915_GEM_USERPTR 0x32 #define LOCAL_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + LOCAL_I915_GEM_USERPTR, struct local_i915_gem_userptr) @@ -767,6 +769,14 @@ #endif } +static bool test_has_secure_batches(struct kgem *kgem) +{ + if (DBG_NO_SECURE_BATCHES) + return false; + + return gem_param(kgem, LOCAL_I915_PARAM_HAS_SECURE_BATCHES) > 0; +} + static int kgem_get_screen_index(struct kgem *kgem) { struct sna *sna = container_of(kgem, struct sna, kgem); @@ -822,6 +832,10 @@ DBG(("%s: can blt to cpu? %d\n", __FUNCTION__, kgem->can_blt_cpu)); + kgem->has_secure_batches = test_has_secure_batches(kgem); + DBG(("%s: can use privileged batchbuffers? %d\n", __FUNCTION__, + kgem->has_secure_batches)); + if (!is_hw_supported(kgem, dev)) { xf86DrvMsg(kgem_get_screen_index(kgem), X_WARNING, "Detected unsupported/dysfunctional hardware, disabling acceleration.\n"); @@ -2147,6 +2161,7 @@ kgem->nbatch = 0; kgem->surface = kgem->batch_size; kgem->mode = KGEM_NONE; + kgem->batch_flags = 0; kgem->flush = 0; kgem->next_request = __kgem_request_alloc(); @@ -2258,7 +2273,7 @@ execbuf.num_cliprects = 0; execbuf.DR1 = 0; execbuf.DR4 = 0; - execbuf.flags = kgem->ring; + execbuf.flags = kgem->ring | kgem->batch_flags; execbuf.rsvd1 = 0; execbuf.rsvd2 = 0; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/kgem.h new/xf86-video-intel-2.20.12/src/sna/kgem.h --- old/xf86-video-intel-2.20.10/src/sna/kgem.h 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/kgem.h 2012-10-20 17:23:26.000000000 +0200 @@ -138,6 +138,9 @@ int16_t count; } vma[NUM_MAP_TYPES]; + uint32_t batch_flags; +#define I915_EXEC_SECURE (1<<9) + uint16_t nbatch; uint16_t surface; uint16_t nexec; @@ -158,6 +161,7 @@ uint32_t has_relaxed_fencing :1; uint32_t has_relaxed_delta :1; uint32_t has_semaphores :1; + uint32_t has_secure_batches :1; uint32_t has_cacheing :1; uint32_t has_llc :1; @@ -510,9 +514,6 @@ if (bo->map == NULL) return bo->tiling == I915_TILING_NONE && bo->domain == DOMAIN_CPU; - if (bo->tiling == I915_TILING_X && !bo->scanout && kgem->has_llc) - return IS_CPU_MAP(bo->map); - return IS_CPU_MAP(bo->map) == !bo->tiling; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_accel.c new/xf86-video-intel-2.20.12/src/sna/sna_accel.c --- old/xf86-video-intel-2.20.10/src/sna/sna_accel.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_accel.c 2012-10-20 17:23:26.000000000 +0200 @@ -2791,6 +2791,7 @@ DBG(("%s: using GPU bo with damage? %d\n", __FUNCTION__, *damage != NULL)); + assert(damage == NULL || !DAMAGE_IS_ALL(*damage)); assert(priv->gpu_bo->proxy == NULL); assert(priv->clear == false); assert(priv->cpu == false); @@ -2859,6 +2860,19 @@ return NULL; } + if (priv->shm) { + assert(!priv->flush); + sna_add_flush_pixmap(sna, priv, priv->cpu_bo); + + /* As we may have flushed and retired,, recheck for busy bo */ + if ((flags & FORCE_GPU) == 0 && !kgem_bo_is_busy(priv->cpu_bo)) + return NULL; + } + if (priv->flush) { + assert(!priv->shm); + sna_add_flush_pixmap(sna, priv, priv->gpu_bo); + } + if (sna_damage_is_all(&priv->cpu_damage, pixmap->drawable.width, pixmap->drawable.height)) { @@ -2873,21 +2887,9 @@ *damage = &priv->cpu_damage; } - if (priv->shm) { - assert(!priv->flush); - sna_add_flush_pixmap(sna, priv, priv->cpu_bo); - - /* As we may have flushed and retired,, recheck for busy bo */ - if ((flags & FORCE_GPU) == 0 && !kgem_bo_is_busy(priv->cpu_bo)) - return NULL; - } - if (priv->flush) { - assert(!priv->shm); - sna_add_flush_pixmap(sna, priv, priv->gpu_bo); - } - DBG(("%s: using CPU bo with damage? %d\n", __FUNCTION__, *damage != NULL)); + assert(damage == NULL || !DAMAGE_IS_ALL(*damage)); assert(priv->clear == false); return priv->cpu_bo; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_blt.c new/xf86-video-intel-2.20.12/src/sna/sna_blt.c --- old/xf86-video-intel-2.20.10/src/sna/sna_blt.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_blt.c 2012-10-20 17:23:26.000000000 +0200 @@ -1899,6 +1899,7 @@ if (tmp->dst.bo == priv->cpu_bo) { DBG(("%s: forcing the stall to overwrite a busy CPU bo\n", __FUNCTION__)); tmp->dst.bo = NULL; + tmp->damage = NULL; } } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_display.c new/xf86-video-intel-2.20.12/src/sna/sna_display.c --- old/xf86-video-intel-2.20.10/src/sna/sna_display.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_display.c 2012-10-20 17:23:26.000000000 +0200 @@ -2717,41 +2717,75 @@ return best_crtc; } -/* Gen6 wait for scan line support */ #define MI_LOAD_REGISTER_IMM (0x22<<23) -/* gen6: Scan lines register */ -#define GEN6_PIPEA_SLC (0x70004) -#define GEN6_PIPEB_SLC (0x71004) +static bool sna_emit_wait_for_scanline_gen7(struct sna *sna, + int pipe, int y1, int y2, + bool full_height) +{ + uint32_t *b; + + if (!sna->kgem.has_secure_batches) + return false; + + assert(y1 >= 0); + assert(y2 > y1); + assert(sna->kgem.mode); -static void sna_emit_wait_for_scanline_gen6(struct sna *sna, + b = kgem_get_batch(&sna->kgem, 16); + b[0] = MI_LOAD_REGISTER_IMM | 1; + b[1] = 0x44050; /* DERRMR */ + b[2] = ~(1 << (3*full_height + pipe*8)); + b[3] = MI_LOAD_REGISTER_IMM | 1; + b[4] = 0xa188; /* FORCEWAKE_MT */ + b[5] = 2 << 16 | 2; + b[6] = MI_LOAD_REGISTER_IMM | 1; + b[7] = 0x70068 + 0x1000 * pipe; + b[8] = (1 << 31) | (1 << 30) | (y1 << 16) | (y2 - 1); + b[9] = MI_WAIT_FOR_EVENT | 1 << (3*full_height + pipe*5); + b[10] = MI_LOAD_REGISTER_IMM | 1; + b[11] = 0xa188; /* FORCEWAKE_MT */ + b[12] = 2 << 16; + b[13] = MI_LOAD_REGISTER_IMM | 1; + b[14] = 0x44050; /* DERRMR */ + b[15] = ~0; + kgem_advance_batch(&sna->kgem, 16); + + sna->kgem.batch_flags |= I915_EXEC_SECURE; + return true; +} + +static bool sna_emit_wait_for_scanline_gen6(struct sna *sna, int pipe, int y1, int y2, bool full_height) { - uint32_t event; uint32_t *b; - assert (y2 > 0); + if (!sna->kgem.has_secure_batches) + return false; - /* We just wait until the trace passes the roi */ - if (pipe == 0) { - pipe = GEN6_PIPEA_SLC; - event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW; - } else { - pipe = GEN6_PIPEB_SLC; - event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; - } + assert(y1 >= 0); + assert(y2 > y1); + assert(sna->kgem.mode); - kgem_set_mode(&sna->kgem, KGEM_RENDER); - b = kgem_get_batch(&sna->kgem, 4); + b = kgem_get_batch(&sna->kgem, 10); b[0] = MI_LOAD_REGISTER_IMM | 1; - b[1] = pipe; - b[2] = y2 - 1; - b[3] = MI_WAIT_FOR_EVENT | event; - kgem_advance_batch(&sna->kgem, 4); + b[1] = 0x44050; /* DERRMR */ + b[2] = ~(1 << (3*full_height + pipe*8)); + b[3] = MI_LOAD_REGISTER_IMM | 1; + b[4] = 0x4f100; /* magic */ + b[5] = (1 << 31) | (1 << 30) | pipe << 29 | (y1 << 16) | (y2 - 1); + b[6] = MI_WAIT_FOR_EVENT | 1 << (3*full_height + pipe*5); + b[7] = MI_LOAD_REGISTER_IMM | 1; + b[8] = 0x44050; /* DERRMR */ + b[9] = ~0; + kgem_advance_batch(&sna->kgem, 10); + + sna->kgem.batch_flags |= I915_EXEC_SECURE; + return true; } -static void sna_emit_wait_for_scanline_gen4(struct sna *sna, +static bool sna_emit_wait_for_scanline_gen4(struct sna *sna, int pipe, int y1, int y2, bool full_height) { @@ -2778,9 +2812,11 @@ b[3] = b[1] = (y1 << 16) | (y2-1); b[4] = MI_WAIT_FOR_EVENT | event; kgem_advance_batch(&sna->kgem, 5); + + return true; } -static void sna_emit_wait_for_scanline_gen2(struct sna *sna, +static bool sna_emit_wait_for_scanline_gen2(struct sna *sna, int pipe, int y1, int y2, bool full_height) { @@ -2805,6 +2841,8 @@ else b[4] = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; kgem_advance_batch(&sna->kgem, 5); + + return true; } bool @@ -2815,15 +2853,12 @@ { bool full_height; int y1, y2, pipe; + bool ret; assert(crtc); assert(to_sna_crtc(crtc)->bo != NULL); assert(pixmap == sna->front); - /* XXX WAIT_EVENT is still causing hangs on SNB */ - if (sna->kgem.gen >= 60) - return false; - /* * Make sure we don't wait for a scanline that will * never occur @@ -2850,14 +2885,18 @@ DBG(("%s: pipe=%d, y1=%d, y2=%d, full_height?=%d\n", __FUNCTION__, pipe, y1, y2, full_height)); - if (sna->kgem.gen >= 60) - sna_emit_wait_for_scanline_gen6(sna, pipe, y1, y2, full_height); + if (sna->kgem.gen >= 80) + ret = false; + else if (sna->kgem.gen >= 70) + ret = sna_emit_wait_for_scanline_gen7(sna, pipe, y1, y2, full_height); + else if (sna->kgem.gen >= 60) + ret =sna_emit_wait_for_scanline_gen6(sna, pipe, y1, y2, full_height); else if (sna->kgem.gen >= 40) - sna_emit_wait_for_scanline_gen4(sna, pipe, y1, y2, full_height); + ret = sna_emit_wait_for_scanline_gen4(sna, pipe, y1, y2, full_height); else - sna_emit_wait_for_scanline_gen2(sna, pipe, y1, y2, full_height); + ret = sna_emit_wait_for_scanline_gen2(sna, pipe, y1, y2, full_height); - return true; + return ret; } void sna_mode_update(struct sna *sna) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_dri.c new/xf86-video-intel-2.20.12/src/sna/sna_dri.c --- old/xf86-video-intel-2.20.10/src/sna/sna_dri.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_dri.c 2012-10-20 17:23:26.000000000 +0200 @@ -525,6 +525,9 @@ void *dst = kgem_bo_map__gtt(&sna->kgem, dst_bo); void *src = kgem_bo_map__gtt(&sna->kgem, src_bo); + if (dst == NULL || src == NULL) + return; + DBG(("%s: src(%d, %d), dst(%d, %d) x %d\n", __FUNCTION__, sx, sy, dx, dy, n)); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_video_overlay.c new/xf86-video-intel-2.20.12/src/sna/sna_video_overlay.c --- old/xf86-video-intel-2.20.10/src/sna/sna_video_overlay.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_video_overlay.c 2012-10-20 17:23:26.000000000 +0200 @@ -532,6 +532,7 @@ return BadAlloc; } + frame.bo->domain = DOMAIN_NONE; sna_video_buffer_fini(sna, video); /* update cliplist */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_video_sprite.c new/xf86-video-intel-2.20.12/src/sna/sna_video_sprite.c --- old/xf86-video-intel-2.20.10/src/sna/sna_video_sprite.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_video_sprite.c 2012-10-20 17:23:26.000000000 +0200 @@ -250,6 +250,7 @@ 0, 0, frame->width << 16, frame->height << 16)) return false; + frame->bo->domain = DOMAIN_NONE; video->plane = plane; return true; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-intel-2.20.10/src/sna/sna_video_textured.c new/xf86-video-intel-2.20.12/src/sna/sna_video_textured.c --- old/xf86-video-intel-2.20.10/src/sna/sna_video_textured.c 2012-10-14 17:34:09.000000000 +0200 +++ new/xf86-video-intel-2.20.12/src/sna/sna_video_textured.c 2012-10-20 17:23:26.000000000 +0200 @@ -275,6 +275,7 @@ } } + kgem_set_mode(&sna->kgem, KGEM_RENDER); if (crtc && video->SyncToVblank != 0 && sna_pixmap_is_scanout(sna, pixmap)) flush = sna_wait_for_scanline(sna, pixmap, crtc, -- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
