Hello community, here is the log from the commit of package leveldb for openSUSE:Factory checked in at 2013-12-30 10:05:23 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/leveldb (Old) and /work/SRC/openSUSE:Factory/.leveldb.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "leveldb" Changes: -------- --- /work/SRC/openSUSE:Factory/leveldb/leveldb.changes 2013-11-14 14:22:15.000000000 +0100 +++ /work/SRC/openSUSE:Factory/.leveldb.new/leveldb.changes 2013-12-30 10:05:24.000000000 +0100 @@ -1,0 +2,5 @@ +Wed Dec 18 17:49:35 CET 2013 - [email protected] + +- add support for other archs (taken from debian, 0001-debian-ports.patch) + +------------------------------------------------------------------- New: ---- 0001-debian-ports.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ leveldb.spec ++++++ --- /var/tmp/diff_new_pack.U5vgvh/_old 2013-12-30 10:05:24.000000000 +0100 +++ /var/tmp/diff_new_pack.U5vgvh/_new 2013-12-30 10:05:24.000000000 +0100 @@ -19,11 +19,12 @@ Name: leveldb Version: 1.14.0 Release: 0 -License: BSD-3-Clause Summary: A key/value-store -Url: http://code.google.com/p/leveldb/ +License: BSD-3-Clause Group: Development/Libraries/C and C++ +Url: http://code.google.com/p/leveldb/ Source: leveldb-%{version}.tar.gz +Patch0: 0001-debian-ports.patch BuildRequires: gcc-c++ BuildRequires: snappy-devel BuildRoot: %{_tmppath}/%{name}-%{version}-build @@ -65,6 +66,7 @@ %prep %setup -q +%patch0 -p1 %build make %{?_smp_flags} OPT="%{optflags}" ++++++ 0001-debian-ports.patch ++++++ Description: Add support for most of Debian architectures Author: Nobuhiro Iwamatsu <[email protected]> --- port/atomic_pointer.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 126 insertions(+), 10 deletions(-) --- leveldb.orig/port/atomic_pointer.h +++ leveldb/port/atomic_pointer.h @@ -38,6 +38,18 @@ #define ARCH_CPU_ARM_FAMILY 1 #elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) #define ARCH_CPU_PPC_FAMILY 1 +#elif defined(__ia64__) +#define ARCH_CPU_IA64_FAMILY 1 +#elif defined(__alpha__) +#define ARCH_CPU_ALPHA_FAMILY 1 +#elif defined(__s390x__) || defined(__s390__) +#define ARCH_CPU_S390_FAMILY 1 +#elif defined(__sparc__) || defined(__sparc64__) +#define ARCH_CPU_SPARC_FAMILY 1 +#elif defined(__sh__) +#define ARCH_CPU_SH_FAMILY 1 +#elif defined(__hppa__) || defined(__parisc__) +#define ARCH_CPU_PARISC_FAMILY 1 #endif namespace leveldb { @@ -50,9 +62,17 @@ namespace port { // http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx #define LEVELDB_HAVE_MEMORY_BARRIER +#define ReadMemoryBarrier MemoryBarrier() +#define WriteMemoryBarrier MemoryBarrier() + // Gcc on x86 #elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__) -inline void MemoryBarrier() { +inline void ReadMemoryBarrier() { + // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on + // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering. + __asm__ __volatile__("" : : : "memory"); +} +inline void WriteMemoryBarrier() { // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering. __asm__ __volatile__("" : : : "memory"); @@ -61,7 +81,12 @@ inline void MemoryBarrier() { // Sun Studio #elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC) -inline void MemoryBarrier() { +inline void ReadMemoryBarrier() { + // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on + // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering. + asm volatile("" : : : "memory"); +} +inline void WriteMemoryBarrier() { // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering. asm volatile("" : : : "memory"); @@ -70,7 +95,10 @@ inline void MemoryBarrier() { // Mac OS #elif defined(OS_MACOSX) -inline void MemoryBarrier() { +inline void ReadMemoryBarrier() { + OSMemoryBarrier(); +} +inline void WriteMemoryBarrier() { OSMemoryBarrier(); } #define LEVELDB_HAVE_MEMORY_BARRIER @@ -88,17 +116,99 @@ typedef void (*LinuxKernelMemoryBarrierF // shows that the extra function call cost is completely negligible on // multi-core devices. // -inline void MemoryBarrier() { +inline void ReadMemoryBarrier() { + (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)(); +} +inline void WriteMemoryBarrier() { (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)(); } #define LEVELDB_HAVE_MEMORY_BARRIER // PPC #elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) -inline void MemoryBarrier() { - // TODO for some powerpc expert: is there a cheaper suitable variant? - // Perhaps by having separate barriers for acquire and release ops. - asm volatile("sync" : : : "memory"); + +inline void ReadMemoryBarrier() { +#ifdef __powerpc64__ + __asm__ __volatile__ ("lwsync" : : : "memory"); +#else + __asm__ __volatile__ ("sync" : : : "memory"); +#endif +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__ ("sync" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + +// IA64 +#elif defined(ARCH_CPU_IA64_FAMILY) +inline void ReadMemoryBarrier() { + __asm__ __volatile__ ("mf" : : : "memory"); +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__ ("mf" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + +// ALPHA +#elif defined(ARCH_CPU_ALPHA_FAMILY) + +inline void ReadMemoryBarrier() { + __asm__ __volatile__("mb" : : : "memory"); +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__("wmb" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + +// S390 +#elif defined(ARCH_CPU_S390_FAMILY) + +inline void ReadMemoryBarrier() { + asm volatile("bcr 15,0" : : : "memory"); +} +inline void WriteMemoryBarrier() { + asm volatile("bcr 15,0" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + +// SPARC +#elif defined(ARCH_CPU_SPARC_FAMILY) + +inline void ReadMemoryBarrier() { + __asm__ __volatile__("" : : : "memory"); +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__("" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + +// SH +#elif defined(ARCH_CPU_SH_FAMILY) +#if defined(__SH4A__) || defined(__SH5__) +inline void ReadMemoryBarrier() { + __asm__ __volatile__ ("synco": : :"memory"); +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__ ("synco": : :"memory"); +} +#else +inline void ReadMemoryBarrier() { + __asm__ __volatile__ ("": : :"memory"); +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__ ("": : :"memory"); +} +#endif +#define LEVELDB_HAVE_MEMORY_BARRIER + +// PARISC +#elif defined(ARCH_CPU_PARISC_FAMILY) + +inline void ReadMemoryBarrier() { + __asm__ __volatile__("" : : : "memory") +} +inline void WriteMemoryBarrier() { + __asm__ __volatile__("" : : : "memory") } #define LEVELDB_HAVE_MEMORY_BARRIER @@ -116,11 +226,11 @@ class AtomicPointer { inline void NoBarrier_Store(void* v) { rep_ = v; } inline void* Acquire_Load() const { void* result = rep_; - MemoryBarrier(); + ReadMemoryBarrier(); return result; } inline void Release_Store(void* v) { - MemoryBarrier(); + WriteMemoryBarrier(); rep_ = v; } }; @@ -217,6 +327,12 @@ class AtomicPointer { #undef ARCH_CPU_X86_FAMILY #undef ARCH_CPU_ARM_FAMILY #undef ARCH_CPU_PPC_FAMILY +#undef ARCH_CPU_IA64_FAMILY +#undef ARCH_CPU_ALPHA_FAMILY +#undef ARCH_CPU_S390_FAMILY +#undef ARCH_CPU_SPARC_FAMILY +#undef ARCH_CPU_SH_FAMILY +#undef ARCH_CPU_PARISC_FAMILY } // namespace port } // namespace leveldb -- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
