Hello community,
here is the log from the commit of package gcc48 for openSUSE:Factory checked
in at 2014-02-13 06:45:28
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/gcc48 (Old)
and /work/SRC/openSUSE:Factory/.gcc48.new (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "gcc48"
Changes:
--------
---
/work/SRC/openSUSE:Factory/gcc48/cross-aarch64-gcc48-icecream-backend.changes
2014-01-11 11:11:09.000000000 +0100
+++
/work/SRC/openSUSE:Factory/.gcc48.new/cross-aarch64-gcc48-icecream-backend.changes
2014-02-13 06:45:29.000000000 +0100
@@ -1,0 +2,31 @@
+Tue Feb 4 16:19:47 UTC 2014 - [email protected]
+
+- stack-protector-aarch64.patch: enable support for -fstack-protector on
+ arm64
+- function-profiling-aarch64.patch: enable support for function profiling
+ on arm64
+
+-------------------------------------------------------------------
+Tue Jan 28 09:09:05 UTC 2014 - [email protected]
+
+- Pull gcc48-ibm-power8.diff from IBM to fix quad-word memory
+ accesses for litte endian power8 for real. [bnc#860405]
+- Revert previous changes to gcc48-ibm-power8.diff.
+
+-------------------------------------------------------------------
+Sun Jan 19 18:15:57 UTC 2014 - [email protected]
+
+- Disable quad-word memory accesses for little endian power8
+ (modified patches: gcc48-ibm-power8.diff)
+- Enable power8 code generation for repos named "power8".
+
+-------------------------------------------------------------------
+Fri Jan 17 11:05:09 UTC 2014 - [email protected]
+
+- Update to gcc-4_8-branch head (r206703).
+ * pulls fixes for PR58139 (ppc64le) and PR59803 (s390x)
+ * reverts change causing x86 ABI breakage
+- gcc48-pr59844.diff: Add backport fixing power8 ppc64le bootstrap issue.
+- gcc48-pr59860.diff: Add backport fixing s390x ICEs.
+
+-------------------------------------------------------------------
@@ -6 +37 @@
- gcc48-ibm-random.diff: Add backport for Power8 support. [fate#315446]
+ gcc48-ibm-power8-other.diff: Add backport for Power8 support. [fate#315446]
cross-armv6hl-gcc48-icecream-backend.changes: same change
cross-armv7hl-gcc48-icecream-backend.changes: same change
cross-hppa-gcc48-icecream-backend.changes: same change
cross-i386-gcc48-icecream-backend.changes: same change
cross-ia64-gcc48-icecream-backend.changes: same change
cross-ppc-gcc48-icecream-backend.changes: same change
cross-ppc64-gcc48-icecream-backend.changes: same change
cross-ppc64le-gcc48-icecream-backend.changes: same change
cross-s390-gcc48-icecream-backend.changes: same change
cross-s390x-gcc48-icecream-backend.changes: same change
cross-x86_64-gcc48-icecream-backend.changes: same change
gcc48-testresults.changes: same change
gcc48.changes: same change
libffi48.changes: same change
libgcj48.changes: same change
Old:
----
gcc-4.8.2-r206511.tar.bz2
New:
----
function-profiling-aarch64.patch
gcc-4.8.2-r206703.tar.bz2
gcc48-ibm-power8-fixes1.diff
gcc48-pr59844.diff
gcc48-pr59860.diff
stack-protector-aarch64.patch
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cross-aarch64-gcc48-icecream-backend.spec ++++++
--- /var/tmp/diff_new_pack.M3wEMW/_old 2014-02-13 06:45:33.000000000 +0100
+++ /var/tmp/diff_new_pack.M3wEMW/_new 2014-02-13 06:45:33.000000000 +0100
@@ -91,7 +91,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
Url: http://gcc.gnu.org/
-Version: 4.8.2+r206511
+Version: 4.8.2+r206703
Release: 0
%define gcc_version %(echo %version | sed 's/+.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -119,6 +119,9 @@
Patch32: libgcj_bc-install.patch
Patch33: m68k-notice-update-cc.patch
Patch34: pr58369.patch
+Patch35: gcc48-pr59860.diff
+Patch36: stack-protector-aarch64.patch
+Patch37: function-profiling-aarch64.patch
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -130,6 +133,8 @@
Patch70: gcc48-ibm-power8.diff
Patch71: gcc48-ibm-power8-testsuite.diff
Patch72: gcc48-ibm-power8-other.diff
+Patch73: gcc48-pr59844.diff
+Patch74: gcc48-ibm-power8-fixes1.diff
# Patches for SAP features
Patch130: sap303956-uchar.diff
@@ -197,6 +202,9 @@
%patch32 -p1
%patch33 -p1
%patch34 -p1
+%patch35
+%patch36 -p1
+%patch37 -p1
%patch51
%patch55
%patch57
@@ -205,6 +213,8 @@
%patch70
%patch71
%patch72
+%patch73
+%patch74
%patch130
#test patching end
@@ -434,9 +444,15 @@
%if "%{TARGET_ARCH}" == "powerpc"
--with-cpu=default32 \
%endif
+%if "%_repository" == "power8"
+ --with-cpu-32=power8 \
+ --with-cpu-64=power8 \
+ --with-tune=power8 \
+%else
--with-cpu-32=power7 \
--with-cpu-64=power7 \
--with-tune=power7 \
+%endif
--enable-secureplt \
--with-long-double-128 \
%if "%{TARGET_ARCH}" == "powerpc64le"
cross-armv6hl-gcc48-icecream-backend.spec: same change
cross-armv7hl-gcc48-icecream-backend.spec: same change
cross-hppa-gcc48-icecream-backend.spec: same change
cross-i386-gcc48-icecream-backend.spec: same change
cross-ia64-gcc48-icecream-backend.spec: same change
cross-ppc-gcc48-icecream-backend.spec: same change
cross-ppc64-gcc48-icecream-backend.spec: same change
cross-ppc64le-gcc48-icecream-backend.spec: same change
cross-s390-gcc48-icecream-backend.spec: same change
cross-s390x-gcc48-icecream-backend.spec: same change
cross-x86_64-gcc48-icecream-backend.spec: same change
gcc48-testresults.spec: same change
++++++ gcc48.spec ++++++
--- /var/tmp/diff_new_pack.M3wEMW/_old 2014-02-13 06:45:34.000000000 +0100
+++ /var/tmp/diff_new_pack.M3wEMW/_new 2014-02-13 06:45:34.000000000 +0100
@@ -205,7 +205,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
Url: http://gcc.gnu.org/
-Version: 4.8.2+r206511
+Version: 4.8.2+r206703
Release: 0
%define gcc_version %(echo %version | sed 's/+.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -259,6 +259,9 @@
Patch32: libgcj_bc-install.patch
Patch33: m68k-notice-update-cc.patch
Patch34: pr58369.patch
+Patch35: gcc48-pr59860.diff
+Patch36: stack-protector-aarch64.patch
+Patch37: function-profiling-aarch64.patch
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -270,6 +273,8 @@
Patch70: gcc48-ibm-power8.diff
Patch71: gcc48-ibm-power8-testsuite.diff
Patch72: gcc48-ibm-power8-other.diff
+Patch73: gcc48-pr59844.diff
+Patch74: gcc48-ibm-power8-fixes1.diff
# Patches for SAP features
Patch130: sap303956-uchar.diff
@@ -1489,6 +1494,9 @@
%patch32 -p1
%patch33 -p1
%patch34 -p1
+%patch35
+%patch36 -p1
+%patch37 -p1
%patch51
%patch55
%patch57
@@ -1497,6 +1505,8 @@
%patch70
%patch71
%patch72
+%patch73
+%patch74
%patch130
#test patching end
@@ -1726,9 +1736,15 @@
%if "%{TARGET_ARCH}" == "powerpc"
--with-cpu=default32 \
%endif
+%if "%_repository" == "power8"
+ --with-cpu-32=power8 \
+ --with-cpu-64=power8 \
+ --with-tune=power8 \
+%else
--with-cpu-32=power7 \
--with-cpu-64=power7 \
--with-tune=power7 \
+%endif
--enable-secureplt \
--with-long-double-128 \
%if "%{TARGET_ARCH}" == "powerpc64le"
++++++ libffi48.spec ++++++
--- /var/tmp/diff_new_pack.M3wEMW/_old 2014-02-13 06:45:34.000000000 +0100
+++ /var/tmp/diff_new_pack.M3wEMW/_new 2014-02-13 06:45:34.000000000 +0100
@@ -222,7 +222,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
Url: http://gcc.gnu.org/
-Version: 4.8.2+r206511
+Version: 4.8.2+r206703
Release: 0
%define gcc_version %(echo %version | sed 's/+.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -276,6 +276,9 @@
Patch32: libgcj_bc-install.patch
Patch33: m68k-notice-update-cc.patch
Patch34: pr58369.patch
+Patch35: gcc48-pr59860.diff
+Patch36: stack-protector-aarch64.patch
+Patch37: function-profiling-aarch64.patch
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -287,6 +290,8 @@
Patch70: gcc48-ibm-power8.diff
Patch71: gcc48-ibm-power8-testsuite.diff
Patch72: gcc48-ibm-power8-other.diff
+Patch73: gcc48-pr59844.diff
+Patch74: gcc48-ibm-power8-fixes1.diff
# Patches for SAP features
Patch130: sap303956-uchar.diff
@@ -493,6 +498,9 @@
%patch32 -p1
%patch33 -p1
%patch34 -p1
+%patch35
+%patch36 -p1
+%patch37 -p1
%patch51
%patch55
%patch57
@@ -501,6 +509,8 @@
%patch70
%patch71
%patch72
+%patch73
+%patch74
%patch130
#test patching end
@@ -730,9 +740,15 @@
%if "%{TARGET_ARCH}" == "powerpc"
--with-cpu=default32 \
%endif
+%if "%_repository" == "power8"
+ --with-cpu-32=power8 \
+ --with-cpu-64=power8 \
+ --with-tune=power8 \
+%else
--with-cpu-32=power7 \
--with-cpu-64=power7 \
--with-tune=power7 \
+%endif
--enable-secureplt \
--with-long-double-128 \
%if "%{TARGET_ARCH}" == "powerpc64le"
libgcj48.spec: same change
++++++ function-profiling-aarch64.patch ++++++
2013-09-30 Venkataramanan Kumar <[email protected]>
* config/aarch64/aarch64.h (MCOUNT_NAME): Define.
(NO_PROFILE_COUNTERS): Likewise.
(PROFILE_HOOK): Likewise.
(FUNCTION_PROFILER): Likewise.
* config/aarch64/aarch64.c (aarch64_function_profiler): Remove.
Index: gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.c
===================================================================
--- gcc-4.8.2-r206703.orig/gcc/config/aarch64/aarch64.c
+++ gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.c
@@ -3647,13 +3647,6 @@ aarch64_print_operand_address (FILE *f,
output_addr_const (f, x);
}
-void
-aarch64_function_profiler (FILE *f ATTRIBUTE_UNUSED,
- int labelno ATTRIBUTE_UNUSED)
-{
- sorry ("function profiling");
-}
-
bool
aarch64_label_mentioned_p (rtx x)
{
Index: gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.h
===================================================================
--- gcc-4.8.2-r206703.orig/gcc/config/aarch64/aarch64.h
+++ gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.h
@@ -758,8 +758,22 @@ do {
\
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
aarch64_print_operand_address (STREAM, X)
-#define FUNCTION_PROFILER(STREAM, LABELNO) \
- aarch64_function_profiler (STREAM, LABELNO)
+#define MCOUNT_NAME "_mcount"
+
+#define NO_PROFILE_COUNTERS 1
+
+/* Emit rtl for profiling. Output assembler code to FILE
+ to call "_mcount" for profiling a function entry. */
+#define PROFILE_HOOK(LABEL) \
+{ \
+ rtx fun,lr; \
+ lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \
+ fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \
+ emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \
+}
+
+/* All the work done in PROFILE_HOOK, but still required. */
+#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
/* For some reason, the Linux headers think they know how to define
these macros. They don't!!! */
Index: gcc-4.8.2-r206703/gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc-4.8.2-r206703.orig/gcc/testsuite/lib/target-supports.exp
+++ gcc-4.8.2-r206703/gcc/testsuite/lib/target-supports.exp
@@ -487,13 +487,6 @@ proc check_profiling_available { test_wh
return 0
}
- # We don't yet support profiling for AArch64.
- if { [istarget aarch64*-*-*]
- && ([lindex $test_what 1] == "-p"
- || [lindex $test_what 1] == "-pg") } {
- return 0
- }
-
# cygwin does not support -p.
if { [istarget *-*-cygwin*] && $test_what == "-p" } {
return 0
++++++ gcc-4.8.2-r206511.tar.bz2 -> gcc-4.8.2-r206703.tar.bz2 ++++++
/work/SRC/openSUSE:Factory/gcc48/gcc-4.8.2-r206511.tar.bz2
/work/SRC/openSUSE:Factory/.gcc48.new/gcc-4.8.2-r206703.tar.bz2 differ: char
11, line 1
++++++ gcc.spec.in ++++++
--- /var/tmp/diff_new_pack.M3wEMW/_old 2014-02-13 06:45:34.000000000 +0100
+++ /var/tmp/diff_new_pack.M3wEMW/_new 2014-02-13 06:45:34.000000000 +0100
@@ -210,7 +210,7 @@
%define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
URL: http://gcc.gnu.org/
-Version: 4.8.2+r206511
+Version: 4.8.2+r206703
Release: 1
%define gcc_version %(echo %version | sed 's/+.*//')
%define gcc_dir_version %(echo %gcc_version | cut -d '.' -f 1-2)
@@ -266,6 +266,9 @@
Patch32: libgcj_bc-install.patch
Patch33: m68k-notice-update-cc.patch
Patch34: pr58369.patch
+Patch35: gcc48-pr59860.diff
+Patch36: stack-protector-aarch64.patch
+Patch37: function-profiling-aarch64.patch
# A set of patches from the RH srpm
Patch51: gcc41-ia64-stack-protector.patch
Patch55: gcc41-java-slow_pthread_self.patch
@@ -277,6 +280,8 @@
Patch70: gcc48-ibm-power8.diff
Patch71: gcc48-ibm-power8-testsuite.diff
Patch72: gcc48-ibm-power8-other.diff
+Patch73: gcc48-pr59844.diff
+Patch74: gcc48-ibm-power8-fixes1.diff
# Patches for SAP features
Patch130: sap303956-uchar.diff
@@ -996,6 +1001,9 @@
%patch32 -p1
%patch33 -p1
%patch34 -p1
+%patch35
+%patch36 -p1
+%patch37 -p1
%patch51
%patch55
%patch57
@@ -1004,6 +1012,8 @@
%patch70
%patch71
%patch72
+%patch73
+%patch74
%patch130
#test patching end
@@ -1233,9 +1243,15 @@
%if "%{TARGET_ARCH}" == "powerpc"
--with-cpu=default32 \
%endif
+%if "%_repository" == "power8"
+ --with-cpu-32=power8 \
+ --with-cpu-64=power8 \
+ --with-tune=power8 \
+%else
--with-cpu-32=power7 \
--with-cpu-64=power7 \
--with-tune=power7 \
+%endif
--enable-secureplt \
--with-long-double-128 \
%if "%{TARGET_ARCH}" == "powerpc64le"
++++++ gcc48-ibm-power8-fixes1.diff ++++++
[gcc]
2014-01-23 Michael Meissner <[email protected]>
PR target/59909
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mquad-memory-atomic. Update -mquad-memory documentation to say
it is only used for non-atomic loads/stores.
* config/rs6000/predicates.md (quad_int_reg_operand): Allow either
-mquad-memory or -mquad-memory-atomic switches.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mquad-memory-atomic to ISA 2.07 support.
* config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch
to separate support of normal quad word memory operations (ldq,
stq) from the atomic quad word memory operations.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support to separate non-atomic quad word operations from atomic
quad word operations. Disable non-atomic quad word operations in
little endian mode so that we don't have to swap words after the
load and before the store.
(quad_load_store_p): Add comment about atomic quad word support.
(rs6000_opt_masks): Add -mquad-memory-atomic to the list of
options printed with -mdebug=reg.
* config/rs6000/rs6000.h (TARGET_SYNC_TI): Use
-mquad-memory-atomic as the test for whether we have quad word
atomic instructions.
(TARGET_SYNC_HI_QI): If either -mquad-memory-atomic,
-mquad-memory, or -mp8-vector are used, allow byte/half-word
atomic operations.
* config/rs6000/sync.md (load_lockedti): Insure that the address
is a proper indexed or indirect address for the lqarx instruction.
On little endian systems, swap the hi/lo registers after the lqarx
instruction.
(load_lockedpti): Use indexed_or_indirect_operand predicate to
insure the address is valid for the lqarx instruction.
(store_conditionalti): Insure that the address is a proper indexed
or indirect address for the stqcrx. instruction. On little endian
systems, swap the hi/lo registers before doing the stqcrx.
instruction.
(store_conditionalpti): Use indexed_or_indirect_operand predicate to
insure the address is valid for the stqcrx. instruction.
* gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what
type of quad memory support is available.
[gcc/testsuite]
2014-01-23 Michael Meissner <[email protected]>
PR target/59909
* gcc.target/powerpc/quad-atomic.c: New file to test power8 quad
word atomic functions at runtime.
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 207020)
+++ gcc/doc/invoke.texi (working copy)
@@ -858,7 +858,9 @@ See RS/6000 and PowerPC Options.
-msave-toc-indirect -mno-save-toc-indirect @gol
-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol
-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol
--mquad-memory -mno-quad-memory}
+-mquad-memory -mno-quad-memory @gol
+-mquad-memory-atomic -mno-quad-memory-atomic @gol
+-mcompat-align-parm -mno-compat-align-parm}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
@@ -17241,8 +17243,8 @@ following options:
-mpopcntb -mpopcntd -mpowerpc64 @gol
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
--mcrypto -mdirect-move -mpower8-fusion -mpower8-vector -mquad-memory @gol
--mcompat-align-parm -mno-compat-align-parm}
+-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
+-mquad-memory -mquad-memory-atomic}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
@@ -17397,10 +17399,18 @@ the vector instructions.
@itemx -mno-quad-memory
@opindex mquad-memory
@opindex mno-quad-memory
-Generate code that uses (does not use) the quad word memory
+Generate code that uses (does not use) the non-atomic quad word memory
instructions. The @option{-mquad-memory} option requires use of
64-bit mode.
+@item -mquad-memory-atomic
+@itemx -mno-quad-memory-atomic
+@opindex mquad-memory-atomic
+@opindex mno-quad-memory-atomic
+Generate code that uses (does not use) the atomic quad word memory
+instructions. The @option{-mquad-memory-atomic} option requires use of
+64-bit mode.
+
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md (revision 207020)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -270,7 +270,7 @@ (define_predicate "quad_int_reg_operand"
{
HOST_WIDE_INT r;
- if (!TARGET_QUAD_MEMORY)
+ if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
return 0;
if (GET_CODE (op) == SUBREG)
@@ -633,6 +633,7 @@ (define_predicate "offsettable_mem_opera
(match_test "offsettable_nonstrict_memref_p (op)")))
;; Return 1 if the operand is suitable for load/store quad memory.
+;; This predicate only checks for non-atomic loads/stores.
(define_predicate "quad_memory_operand"
(match_code "mem")
{
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def (revision 207020)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -53,7 +53,8 @@
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_HTM \
- | OPTION_MASK_QUAD_MEMORY)
+ | OPTION_MASK_QUAD_MEMORY \
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c (revision 207020)
+++ gcc/config/rs6000/rs6000-c.c (working copy)
@@ -337,6 +337,10 @@ rs6000_target_modify_macros (bool define
rs6000_define_or_undefine_macro (define_p, "__HTM__");
if ((flags & OPTION_MASK_P8_VECTOR) != 0)
rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
+ if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
+ if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
+ rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
if ((flags & OPTION_MASK_CRYPTO) != 0)
rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 207020)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -556,7 +556,11 @@ Use ISA 2.07 transactional memory (HTM)
mquad-memory
Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
-Generate the quad word memory instructions (lq/stq/lqarx/stqcx).
+Generate the quad word memory instructions (lq/stq).
+
+mquad-memory-atomic
+Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
+Generate the quad word memory atomic instructions (lqarx/stqcx).
mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(1) Save
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 207020)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -3317,14 +3317,37 @@ rs6000_option_override_internal (bool gl
/* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
silently turn off quad memory mode. */
- if (TARGET_QUAD_MEMORY && !TARGET_POWERPC64)
+ if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
{
if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
warning (0, N_("-mquad-memory requires 64-bit mode"));
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
+ warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
+
+ rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC);
+ }
+
+ /* Non-atomic quad memory load/store are disabled for little endian, since
+ the words are reversed, but atomic operations can still be done by
+ swapping the words. */
+ if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
+ warning (0, N_("-mquad-memory is not available in little endian mode"));
+
rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
}
+ /* Assume if the user asked for normal quad memory instructions, they want
+ the atomic versions as well, unless they explicity told us not to use quad
+ word atomic instructions. */
+ if (TARGET_QUAD_MEMORY
+ && !TARGET_QUAD_MEMORY_ATOMIC
+ && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
+ rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
+
/* Enable power8 fusion if we are tuning for power8, even if we aren't
generating power8 instructions. */
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
@@ -5875,7 +5898,8 @@ direct_move_p (rtx op0, rtx op1)
return false;
}
-/* Return true if this is a load or store quad operation. */
+/* Return true if this is a load or store quad operation. This function does
+ not handle the atomic quad memory instructions. */
bool
quad_load_store_p (rtx op0, rtx op1)
@@ -30675,6 +30699,7 @@ static struct rs6000_opt_mask const rs60
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
+ { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "string", OPTION_MASK_STRING, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 207020)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -524,8 +524,11 @@ extern int rs6000_vector_align[];
/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
in power7, so conditionalize them on p8 features. TImode syncs need quad
memory support. */
-#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY || TARGET_DIRECT_MOVE)
-#define TARGET_SYNC_TI TARGET_QUAD_MEMORY
+#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
+ || TARGET_QUAD_MEMORY_ATOMIC \
+ || TARGET_DIRECT_MOVE)
+
+#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
to allocate the SDmode stack slot to get the value into the proper location
Index: gcc/config/rs6000/sync.md
===================================================================
--- gcc/config/rs6000/sync.md (revision 207020)
+++ gcc/config/rs6000/sync.md (working copy)
@@ -204,25 +204,46 @@ (define_insn "load_locked<QHI:mode>_si"
"<QHI:larx> %0,%y1"
[(set_attr "type" "load_l")])
-;; Use PTImode to get even/odd register pairs
+;; Use PTImode to get even/odd register pairs.
+;; Use a temporary register to force getting an even register for the
+;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
+;; copy on big endian systems.
+
+;; On little endian systems where non-atomic quad word load/store instructions
+;; are not used, the address can be register+offset, so make sure the address
+;; is indexed or indirect before register allocation.
+
(define_expand "load_lockedti"
[(use (match_operand:TI 0 "quad_int_reg_operand" ""))
(use (match_operand:TI 1 "memory_operand" ""))]
"TARGET_SYNC_TI"
{
- /* Use a temporary register to force getting an even register for the
- lqarx/stqcrx. instructions. Normal optimizations will eliminate this
- extra copy. */
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
rtx pti = gen_reg_rtx (PTImode);
- emit_insn (gen_load_lockedpti (pti, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (TImode, pti));
+
+ if (!indexed_or_indirect_operand (op1, TImode))
+ {
+ rtx old_addr = XEXP (op1, 0);
+ rtx new_addr = force_reg (Pmode, old_addr);
+ operands[1] = op1 = change_address (op1, TImode, new_addr);
+ }
+
+ emit_insn (gen_load_lockedpti (pti, op1));
+ if (WORDS_BIG_ENDIAN)
+ emit_move_insn (op0, gen_lowpart (TImode, pti));
+ else
+ {
+ emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti));
+ emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti));
+ }
DONE;
})
(define_insn "load_lockedpti"
[(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
(unspec_volatile:PTI
- [(match_operand:TI 1 "memory_operand" "Z")] UNSPECV_LL))]
+ [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
"TARGET_SYNC_TI
&& !reg_mentioned_p (operands[0], operands[1])
&& quad_int_reg_operand (operands[0], PTImode)"
@@ -238,6 +259,14 @@ (define_insn "store_conditional<mode>"
"<stcx> %2,%y1"
[(set_attr "type" "store_c")])
+;; Use a temporary register to force getting an even register for the
+;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
+;; copy on big endian systems.
+
+;; On little endian systems where non-atomic quad word load/store instructions
+;; are not used, the address can be register+offset, so make sure the address
+;; is indexed or indirect before register allocation.
+
(define_expand "store_conditionalti"
[(use (match_operand:CC 0 "cc_reg_operand" ""))
(use (match_operand:TI 1 "memory_operand" ""))
@@ -247,21 +276,36 @@ (define_expand "store_conditionalti"
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx pti_op1 = change_address (op1, PTImode, XEXP (op1, 0));
- rtx pti_op2 = gen_reg_rtx (PTImode);
+ rtx addr = XEXP (op1, 0);
+ rtx pti_mem;
+ rtx pti_reg;
+
+ if (!indexed_or_indirect_operand (op1, TImode))
+ {
+ rtx new_addr = force_reg (Pmode, addr);
+ operands[1] = op1 = change_address (op1, TImode, new_addr);
+ addr = new_addr;
+ }
+
+ pti_mem = change_address (op1, PTImode, addr);
+ pti_reg = gen_reg_rtx (PTImode);
+
+ if (WORDS_BIG_ENDIAN)
+ emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));
+ else
+ {
+ emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode,
op2));
+ emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode,
op2));
+ }
- /* Use a temporary register to force getting an even register for the
- lqarx/stqcrx. instructions. Normal optimizations will eliminate this
- extra copy. */
- emit_move_insn (pti_op2, gen_lowpart (PTImode, op2));
- emit_insn (gen_store_conditionalpti (op0, pti_op1, pti_op2));
+ emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));
DONE;
})
(define_insn "store_conditionalpti"
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
- (set (match_operand:PTI 1 "memory_operand" "=Z")
+ (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")
(match_operand:PTI 2 "quad_int_reg_operand" "r"))]
"TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
"stqcx. %2,%y1"
++++++ gcc48-pr59844.diff ++++++
2014-01-16 Michael Meissner <[email protected]>
PR target/59844
* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
endian support, remove tests for WORDS_BIG_ENDIAN.
(p8_mfvsrd_3_<mode>): Likewise.
(reload_gpr_from_vsx<mode>): Likewise.
(reload_gpr_from_vsxsf): Likewise.
(p8_mfvsrd_4_disf): Likewise.
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 206667)
+++ gcc/config/rs6000/rs6000.md (revision 206668)
@@ -9972,7 +9972,7 @@ (define_insn_and_split "reload_vsx_from_
(unspec:SF [(match_operand:SF 1 "register_operand" "r")]
UNSPEC_P8V_RELOAD_FROM_GPR))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -9999,7 +9999,7 @@ (define_insn "p8_mfvsrd_3_<mode>"
[(set (match_operand:DF 0 "register_operand" "=r")
(unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"mfvsrd %0,%x1"
[(set_attr "type" "mftgpr")])
@@ -10009,7 +10009,7 @@ (define_insn_and_split "reload_gpr_from_
[(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -10036,7 +10036,7 @@ (define_insn_and_split "reload_gpr_from_
(unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -10058,7 +10058,7 @@ (define_insn "p8_mfvsrd_4_disf"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"mfvsrd %0,%x1"
[(set_attr "type" "mftgpr")])
++++++ gcc48-pr59860.diff ++++++
2014-01-17 Richard Biener <[email protected]>
PR middle-end/59860
* builtins.c (fold_builtin_strcat): Remove case better handled
by tree-ssa-strlen.c.
* gcc.dg/pr59860.c: New testcase.
Index: gcc/testsuite/gcc.dg/pr59860.c
===================================================================
*** gcc/testsuite/gcc.dg/pr59860.c (revision 0)
--- gcc/testsuite/gcc.dg/pr59860.c (working copy)
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O" } */
+
+ extern __inline __attribute__ ((__always_inline__)) __attribute__
((__gnu_inline__)) __attribute__ ((__artificial__)) char * __attribute__
((__nothrow__ , __leaf__))
+ strcat (char *__restrict __dest, const char *__restrict __src)
+ {
+ return __builtin___strcat_chk (__dest, __src, __builtin_object_size
(__dest, 2 > 1));
+ }
+ static char raw_decode;
+ void foo (char **argv, char *outfilename)
+ {
+ if (**argv == 'r')
+ raw_decode = 1;
+ strcat (outfilename, raw_decode ? ".raw" : ".wav");
+ }
Index: gcc/builtins.c
===================================================================
*** gcc/builtins.c (revision 206772)
--- gcc/builtins.c (working copy)
*************** fold_builtin_strcat (location_t loc ATTR
*** 11759,11775 ****
if (!strlen_fn || !strcpy_fn)
return NULL_TREE;
! /* If we don't have a movstr we don't want to emit an strcpy
! call. We have to do that if the length of the source string
! isn't computable (in that case we can use memcpy probably
! later expanding to a sequence of mov instructions). If we
! have movstr instructions we can emit strcpy calls. */
! if (!HAVE_movstr)
! {
! tree len = c_strlen (src, 1);
! if (! len || TREE_SIDE_EFFECTS (len))
! return NULL_TREE;
! }
/* Stabilize the argument list. */
dst = builtin_save_expr (dst);
--- 11759,11769 ----
if (!strlen_fn || !strcpy_fn)
return NULL_TREE;
! /* If the length of the source string isn't computable don't
! split strcat into strlen and strcpy. */
! tree len = c_strlen (src, 1);
! if (! len || TREE_SIDE_EFFECTS (len))
! return NULL_TREE;
/* Stabilize the argument list. */
dst = builtin_save_expr (dst);
++++++ stack-protector-aarch64.patch ++++++
2013-11-13 Christophe Lyon <[email protected]>
* config/aarch64/aarch64.h (FRAME_GROWS_DOWNWARD): Define to 1.
* config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
Update offset calculations.
Index: gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.c
===================================================================
--- gcc-4.8.2-r206703.orig/gcc/config/aarch64/aarch64.c
+++ gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.c
@@ -3919,7 +3919,7 @@ aarch64_initial_elimination_offset (unsi
return offset - crtl->outgoing_args_size;
if (from == FRAME_POINTER_REGNUM)
- return cfun->machine->frame.saved_regs_size;
+ return cfun->machine->frame.saved_regs_size + get_frame_size ();
}
if (to == STACK_POINTER_REGNUM)
@@ -3928,6 +3928,7 @@ aarch64_initial_elimination_offset (unsi
{
HOST_WIDE_INT elim = crtl->outgoing_args_size
+ cfun->machine->frame.saved_regs_size
+ + get_frame_size ()
- cfun->machine->frame.fp_lr_offset;
elim = AARCH64_ROUND_UP (elim, STACK_BOUNDARY / BITS_PER_UNIT);
return elim;
Index: gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.h
===================================================================
--- gcc-4.8.2-r206703.orig/gcc/config/aarch64/aarch64.h
+++ gcc-4.8.2-r206703/gcc/config/aarch64/aarch64.h
@@ -475,7 +475,7 @@ extern enum aarch64_processor aarch64_tu
/* Stack layout; function entry, exit and calling. */
#define STACK_GROWS_DOWNWARD 1
-#define FRAME_GROWS_DOWNWARD 0
+#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
--
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